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llvm-project/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

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[ARM] GlobalISel: Select add i32, i32 Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
2016-12-16 20:54:46 +08:00
# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
[ARM] GlobalISel: Support i1 add and ABI extensions Add support for: * i1 add * i1 function arguments, if passed through registers * i1 returns, with ABI signext/zeroext Differential Revision: https://reviews.llvm.org/D27706 llvm-svn: 293035
2017-01-25 16:47:40 +08:00
define void @test_zext_s1() { ret void }
define void @test_sext_s1() { ret void }
[ARM] GlobalISel: Support i8/i16 ABI extensions At the moment, this means supporting the signext/zeroext attribute on the return type of the function. For function arguments, signext/zeroext should be handled by the caller, so there's nothing for us to do until we start lowering calls. Note that this does not include support for other extensions (i8 to i16), those will be added later. Differential Revision: https://reviews.llvm.org/D27705 llvm-svn: 293034
2017-01-25 16:10:40 +08:00
define void @test_sext_s8() { ret void }
define void @test_zext_s16() { ret void }
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
define void @test_add_s8() { ret void }
define void @test_add_s16() { ret void }
define void @test_add_s32() { ret void }
[ARM] GlobalISel: Add FPR reg bank Add a register bank for floating point values and select simple instructions using them (add, copies from GPR). This assumes that the hardware can cope with a single precision add (VADDS) instruction, so the legalizer will treat G_FADD as legal and the instruction selector will refuse to select if the hardware doesn't support it. In the future we'll want to be more careful about this, and legalize to libcalls if we have to use soft float. llvm-svn: 294442
2017-02-08 21:23:04 +08:00
define void @test_fadd_s32() #0 { ret void }
[ARM] GlobalISel: Select double G_FADD and copies Just use VADDD if available, bail out if not. llvm-svn: 295309
2017-02-16 20:19:52 +08:00
define void @test_fadd_s64() #0 { ret void }
[ARM] GlobalISel: Add FPR reg bank Add a register bank for floating point values and select simple instructions using them (add, copies from GPR). This assumes that the hardware can cope with a single precision add (VADDS) instruction, so the legalizer will treat G_FADD as legal and the instruction selector will refuse to select if the hardware doesn't support it. In the future we'll want to be more careful about this, and legalize to libcalls if we have to use soft float. llvm-svn: 294442
2017-02-08 21:23:04 +08:00
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
define void @test_load_from_stack() { ret void }
[ARM] GlobalISel: Add FPR reg bank Add a register bank for floating point values and select simple instructions using them (add, copies from GPR). This assumes that the hardware can cope with a single precision add (VADDS) instruction, so the legalizer will treat G_FADD as legal and the instruction selector will refuse to select if the hardware doesn't support it. In the future we'll want to be more careful about this, and legalize to libcalls if we have to use soft float. llvm-svn: 294442
2017-02-08 21:23:04 +08:00
[ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACT Since they're only used for passing around double precision floating point values into the general purpose registers, we'll lower them to VMOVDRR and VMOVRRD. llvm-svn: 295310
2017-02-16 20:19:57 +08:00
define void @test_soft_fp_double() #0 { ret void }
Fix test to work on swift/cyclone too I forgot to remove the neonfp target feature from the test, which means we'd have trouble selecting VADDS on targets that have neonfp enabled by default. llvm-svn: 294451
2017-02-08 22:23:30 +08:00
attributes #0 = { "target-features"="+vfp2,-neonfp" }
[ARM] GlobalISel: Select add i32, i32 Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
2016-12-16 20:54:46 +08:00
...
---
[ARM] GlobalISel: Support i1 add and ABI extensions Add support for: * i1 add * i1 function arguments, if passed through registers * i1 returns, with ABI signext/zeroext Differential Revision: https://reviews.llvm.org/D27706 llvm-svn: 293035
2017-01-25 16:47:40 +08:00
name: test_zext_s1
# CHECK-LABEL: name: test_zext_s1
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s1) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = G_ZEXT %0(s1)
; CHECK: [[VREGEXT:%[0-9]+]] = ANDri [[VREGX]], 1, 14, _, _
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_sext_s1
# CHECK-LABEL: name: test_sext_s1
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s1) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = G_SEXT %0(s1)
; CHECK: [[VREGAND:%[0-9]+]] = ANDri [[VREGX]], 1, 14, _, _
; CHECK: [[VREGEXT:%[0-9]+]] = RSBri [[VREGAND]], 0, 14, _, _
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
[ARM] GlobalISel: Support i8/i16 ABI extensions At the moment, this means supporting the signext/zeroext attribute on the return type of the function. For function arguments, signext/zeroext should be handled by the caller, so there's nothing for us to do until we start lowering calls. Note that this does not include support for other extensions (i8 to i16), those will be added later. Differential Revision: https://reviews.llvm.org/D27705 llvm-svn: 293034
2017-01-25 16:10:40 +08:00
---
name: test_sext_s8
# CHECK-LABEL: name: test_sext_s8
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s8) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = G_SEXT %0(s8)
; CHECK: [[VREGEXT:%[0-9]+]] = SXTB [[VREGX]], 0, 14, _
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_zext_s16
# CHECK-LABEL: name: test_zext_s16
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s16) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = G_ZEXT %0(s16)
; CHECK: [[VREGEXT:%[0-9]+]] = UXTH [[VREGX]], 0, 14, _
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
name: test_add_s8
# CHECK-LABEL: name: test_add_s8
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
body: |
bb.0:
liveins: %r0, %r1
%0(s8) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
[ARM] GlobalISel: Allow i8 and i16 adds Teach the instruction selector and legalizer that it's ok to have adds with 8 or 16-bit integers. This is the second part of https://reviews.llvm.org/D27704 llvm-svn: 290105
2016-12-19 22:07:56 +08:00
%1(s8) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s8) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
%r0 = COPY %2(s8)
; CHECK: %r0 = COPY [[VREGSUM]]
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_add_s16
# CHECK-LABEL: name: test_add_s16
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
body: |
bb.0:
liveins: %r0, %r1
%0(s16) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
[ARM] GlobalISel: Allow i8 and i16 adds Teach the instruction selector and legalizer that it's ok to have adds with 8 or 16-bit integers. This is the second part of https://reviews.llvm.org/D27704 llvm-svn: 290105
2016-12-19 22:07:56 +08:00
%1(s16) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s16) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
%r0 = COPY %2(s16)
; CHECK: %r0 = COPY [[VREGSUM]]
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_add_s32
# CHECK-LABEL: name: test_add_s32
[ARM] GlobalISel: Select add i32, i32 Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
2016-12-16 20:54:46 +08:00
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
[ARM] GlobalISel: Minor style fixup in test llvm-svn: 290107
2016-12-19 22:08:06 +08:00
# CHECK: id: 0, class: gpr
# CHECK: id: 1, class: gpr
# CHECK: id: 2, class: gpr
[ARM] GlobalISel: Select add i32, i32 Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
2016-12-16 20:54:46 +08:00
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
---
[ARM] GlobalISel: Add FPR reg bank Add a register bank for floating point values and select simple instructions using them (add, copies from GPR). This assumes that the hardware can cope with a single precision add (VADDS) instruction, so the legalizer will treat G_FADD as legal and the instruction selector will refuse to select if the hardware doesn't support it. In the future we'll want to be more careful about this, and legalize to libcalls if we have to use soft float. llvm-svn: 294442
2017-02-08 21:23:04 +08:00
name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
# CHECK: id: 0, class: spr
# CHECK: id: 1, class: spr
# CHECK: id: 2, class: spr
body: |
bb.0:
liveins: %s0, %s1
%0(s32) = COPY %s0
; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
%1(s32) = COPY %s1
; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
%2(s32) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]] = VADDS [[VREGX]], [[VREGY]], 14, _
%s0 = COPY %2(s32)
; CHECK: %s0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %s0
; CHECK: BX_RET 14, _, implicit %s0
...
---
[ARM] GlobalISel: Select double G_FADD and copies Just use VADDD if available, bail out if not. llvm-svn: 295309
2017-02-16 20:19:52 +08:00
name: test_fadd_s64
# CHECK-LABEL: name: test_fadd_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
# CHECK: id: 0, class: dpr
# CHECK: id: 1, class: dpr
# CHECK: id: 2, class: dpr
body: |
bb.0:
liveins: %d0, %d1
%0(s64) = COPY %d0
; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
%1(s64) = COPY %d1
; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
%2(s64) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]] = VADDD [[VREGX]], [[VREGY]], 14, _
%d0 = COPY %2(s64)
; CHECK: %d0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %d0
; CHECK: BX_RET 14, _, implicit %d0
...
---
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
name: test_load_from_stack
# CHECK-LABEL: name: test_load_from_stack
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
[ARM] GlobalISel: Add more checks to test llvm-svn: 290108
2016-12-19 22:08:11 +08:00
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
# CHECK-DAG: id: 3, class: gpr
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
fixedStack:
[ARM] GlobalISel: Load i1, i8 and i16 args from stack Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
2017-01-26 17:20:47 +08:00
- { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false }
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
- { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
[ARM] GlobalISel: Load i1, i8 and i16 args from stack Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
2017-01-26 17:20:47 +08:00
# CHECK-DAG: id: [[FI1:[0-9]+]], offset: 0
# CHECK-DAG: id: [[FI32:[0-9]+]], offset: 8
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
body: |
bb.0:
liveins: %r0, %r1, %r2, %r3
%0(p0) = G_FRAME_INDEX %fixed-stack.2
[ARM] GlobalISel: Load i1, i8 and i16 args from stack Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
2017-01-26 17:20:47 +08:00
; CHECK: [[FI32VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
%1(s32) = G_LOAD %0(p0)
[ARM] GlobalISel: Load i1, i8 and i16 args from stack Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
2017-01-26 17:20:47 +08:00
; CHECK: {{%[0-9]+}} = LDRi12 [[FI32VREG]], 0, 14, _
%2(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[FI1VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI1]], 0, 14, _, _
%3(s1) = G_LOAD %2(p0)
; CHECK: {{%[0-9]+}} = LDRBi12 [[FI1VREG]], 0, 14, _
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
BX_RET 14, _
; CHECK: BX_RET 14, _
...
[ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACT Since they're only used for passing around double precision floating point values into the general purpose registers, we'll lower them to VMOVDRR and VMOVRRD. llvm-svn: 295310
2017-02-16 20:19:57 +08:00
---
name: test_soft_fp_double
# CHECK-LABEL: name: test_soft_fp_double
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: fprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
# CHECK-DAG: id: {{[0-9]+}}, class: gpr
# CHECK-DAG: id: {{[0-9]+}}, class: gpr
# CHECK-DAG: id: {{[0-9]+}}, class: gpr
# CHECK-DAG: id: {{[0-9]+}}, class: gpr
# CHECK-DAG: id: [[DREG:[0-9]+]], class: dpr
body: |
bb.0:
liveins: %r0, %r1, %r2, %r3
%0(s32) = COPY %r2
; CHECK: [[IN1:%[0-9]+]] = COPY %r2
%1(s32) = COPY %r3
; CHECK: [[IN2:%[0-9]+]] = COPY %r3
%2(s64) = G_SEQUENCE %0(s32), 0, %1(s32), 1
; CHECK: %[[DREG]] = VMOVDRR [[IN1]], [[IN2]]
%3(s32), %4(s32) = G_EXTRACT %2(s64), 0, 32
; CHECK: [[OUT1:%[0-9]+]], [[OUT2:%[0-9]+]] = VMOVRRD %[[DREG]]
%r0 = COPY %3
; CHECK: %r0 = COPY [[OUT1]]
%r1 = COPY %4
; CHECK: %r1 = COPY [[OUT2]]
BX_RET 14, _, implicit %r0, implicit %r1
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
...