forked from OSchip/llvm-project
141 lines
5.1 KiB
Plaintext
141 lines
5.1 KiB
Plaintext
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||
|
|
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s
|
||
|
|
|
||
|
|
---
|
||
|
|
name: smed3_s32_vvv
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0, $vgpr1, $vgpr2
|
||
|
|
|
||
|
|
; GFX6-LABEL: name: smed3_s32_vvv
|
||
|
|
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||
|
|
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||
|
|
; GFX6: [[V_MED3_I32_:%[0-9]+]]:vgpr_32 = V_MED3_I32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
|
||
|
|
; GFX6: S_ENDPGM 0, implicit [[V_MED3_I32_]]
|
||
|
|
%0:vgpr(s32) = COPY $vgpr0
|
||
|
|
%1:vgpr(s32) = COPY $vgpr1
|
||
|
|
%2:vgpr(s32) = COPY $vgpr2
|
||
|
|
%3:vgpr(s32) = G_SMAX %0, %1
|
||
|
|
%4:vgpr(s32) = G_SMIN %0, %1
|
||
|
|
%5:vgpr(s32) = G_SMAX %4, %2
|
||
|
|
%6:vgpr(s32) = G_SMIN %3, %5
|
||
|
|
S_ENDPGM 0, implicit %6
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: smed3_s32_sss
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $sgpr1, $sgpr2
|
||
|
|
|
||
|
|
; GFX6-LABEL: name: smed3_s32_sss
|
||
|
|
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||
|
|
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||
|
|
; GFX6: [[S_MAX_I32_:%[0-9]+]]:sreg_32 = S_MAX_I32 [[COPY]], [[COPY1]], implicit-def $scc
|
||
|
|
; GFX6: [[S_MIN_I32_:%[0-9]+]]:sreg_32 = S_MIN_I32 [[COPY]], [[COPY1]], implicit-def $scc
|
||
|
|
; GFX6: [[S_MAX_I32_1:%[0-9]+]]:sreg_32 = S_MAX_I32 [[S_MIN_I32_]], [[COPY2]], implicit-def $scc
|
||
|
|
; GFX6: [[S_MIN_I32_1:%[0-9]+]]:sreg_32 = S_MIN_I32 [[S_MAX_I32_]], [[S_MAX_I32_1]], implicit-def $scc
|
||
|
|
; GFX6: S_ENDPGM 0, implicit [[S_MIN_I32_1]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s32) = COPY $sgpr1
|
||
|
|
%2:sgpr(s32) = COPY $sgpr2
|
||
|
|
%3:sgpr(s32) = G_SMAX %0, %1
|
||
|
|
%4:sgpr(s32) = G_SMIN %0, %1
|
||
|
|
%5:sgpr(s32) = G_SMAX %4, %2
|
||
|
|
%6:sgpr(s32) = G_SMIN %3, %5
|
||
|
|
S_ENDPGM 0, implicit %6
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: smed3_s32_vvv_multiuse0
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0, $vgpr1, $vgpr2
|
||
|
|
|
||
|
|
; GFX6-LABEL: name: smed3_s32_vvv_multiuse0
|
||
|
|
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||
|
|
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||
|
|
; GFX6: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||
|
|
; GFX6: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||
|
|
; GFX6: [[V_MAX_I32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[V_MIN_I32_e64_]], [[COPY2]], implicit $exec
|
||
|
|
; GFX6: [[V_MIN_I32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[V_MAX_I32_e64_]], [[V_MAX_I32_e64_1]], implicit $exec
|
||
|
|
; GFX6: S_ENDPGM 0, implicit [[V_MIN_I32_e64_1]], implicit [[V_MAX_I32_e64_]]
|
||
|
|
%0:vgpr(s32) = COPY $vgpr0
|
||
|
|
%1:vgpr(s32) = COPY $vgpr1
|
||
|
|
%2:vgpr(s32) = COPY $vgpr2
|
||
|
|
%3:vgpr(s32) = G_SMAX %0, %1
|
||
|
|
%4:vgpr(s32) = G_SMIN %0, %1
|
||
|
|
%5:vgpr(s32) = G_SMAX %4, %2
|
||
|
|
%6:vgpr(s32) = G_SMIN %3, %5
|
||
|
|
S_ENDPGM 0, implicit %6, implicit %3
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: smed3_s32_vvv_multiuse1
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0, $vgpr1, $vgpr2
|
||
|
|
|
||
|
|
; GFX6-LABEL: name: smed3_s32_vvv_multiuse1
|
||
|
|
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||
|
|
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||
|
|
; GFX6: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||
|
|
; GFX6: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||
|
|
; GFX6: [[V_MAX_I32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[V_MIN_I32_e64_]], [[COPY2]], implicit $exec
|
||
|
|
; GFX6: [[V_MIN_I32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[V_MAX_I32_e64_]], [[V_MAX_I32_e64_1]], implicit $exec
|
||
|
|
; GFX6: S_ENDPGM 0, implicit [[V_MIN_I32_e64_1]], implicit [[V_MIN_I32_e64_]]
|
||
|
|
%0:vgpr(s32) = COPY $vgpr0
|
||
|
|
%1:vgpr(s32) = COPY $vgpr1
|
||
|
|
%2:vgpr(s32) = COPY $vgpr2
|
||
|
|
%3:vgpr(s32) = G_SMAX %0, %1
|
||
|
|
%4:vgpr(s32) = G_SMIN %0, %1
|
||
|
|
%5:vgpr(s32) = G_SMAX %4, %2
|
||
|
|
%6:vgpr(s32) = G_SMIN %3, %5
|
||
|
|
S_ENDPGM 0, implicit %6, implicit %4
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: smed3_s32_vvv_multiuse2
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0, $vgpr1, $vgpr2
|
||
|
|
|
||
|
|
; GFX6-LABEL: name: smed3_s32_vvv_multiuse2
|
||
|
|
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||
|
|
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||
|
|
; GFX6: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||
|
|
; GFX6: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||
|
|
; GFX6: [[V_MAX_I32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[V_MIN_I32_e64_]], [[COPY2]], implicit $exec
|
||
|
|
; GFX6: [[V_MIN_I32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[V_MAX_I32_e64_]], [[V_MAX_I32_e64_1]], implicit $exec
|
||
|
|
; GFX6: S_ENDPGM 0, implicit [[V_MIN_I32_e64_1]], implicit [[V_MAX_I32_e64_1]]
|
||
|
|
%0:vgpr(s32) = COPY $vgpr0
|
||
|
|
%1:vgpr(s32) = COPY $vgpr1
|
||
|
|
%2:vgpr(s32) = COPY $vgpr2
|
||
|
|
%3:vgpr(s32) = G_SMAX %0, %1
|
||
|
|
%4:vgpr(s32) = G_SMIN %0, %1
|
||
|
|
%5:vgpr(s32) = G_SMAX %4, %2
|
||
|
|
%6:vgpr(s32) = G_SMIN %3, %5
|
||
|
|
S_ENDPGM 0, implicit %6, implicit %5
|
||
|
|
...
|