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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir

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AMDGPU/GlobalISel: Fix import of s_abs_i32 pattern
2020-01-07 23:22:06 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
---
name: smax_neg_abs_pattern_s32_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; GFX6-LABEL: name: smax_neg_abs_pattern_s32_ss
; GFX6: liveins: $sgpr0
; GFX6: %src0:sreg_32 = COPY $sgpr0
; GFX6: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX6: S_ENDPGM 0, implicit %smax
; GFX9-LABEL: name: smax_neg_abs_pattern_s32_ss
; GFX9: liveins: $sgpr0
; GFX9: %src0:sreg_32 = COPY $sgpr0
; GFX9: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX9: S_ENDPGM 0, implicit %smax
%src0:sgpr(s32) = COPY $sgpr0
%zero:sgpr(s32) = G_CONSTANT i32 0
%ineg:sgpr(s32) = G_SUB %zero, %src0
%smax:sgpr(s32) = G_SMAX %src0, %ineg
S_ENDPGM 0, implicit %smax
...
---
name: smax_neg_abs_pattern_s32_ss_commute
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; GFX6-LABEL: name: smax_neg_abs_pattern_s32_ss_commute
; GFX6: liveins: $sgpr0
; GFX6: %src0:sreg_32 = COPY $sgpr0
; GFX6: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX6: S_ENDPGM 0, implicit %smax
; GFX9-LABEL: name: smax_neg_abs_pattern_s32_ss_commute
; GFX9: liveins: $sgpr0
; GFX9: %src0:sreg_32 = COPY $sgpr0
; GFX9: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX9: S_ENDPGM 0, implicit %smax
%src0:sgpr(s32) = COPY $sgpr0
%zero:sgpr(s32) = G_CONSTANT i32 0
%ineg:sgpr(s32) = G_SUB %zero, %src0
%smax:sgpr(s32) = G_SMAX %ineg, %src0
S_ENDPGM 0, implicit %smax
...
---
name: smax_neg_abs_pattern_s32_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GFX6-LABEL: name: smax_neg_abs_pattern_s32_vv
; GFX6: liveins: $vgpr0
; GFX6: %src0:vgpr_32 = COPY $vgpr0
; GFX6: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
AMDGPU: Rename add/sub with carry out instructions The hardware has created a real mess in the naming for add/sub, which have been renamed basically every generation. Switch the carry out pseudos to have the gfx9/gfx10 names. We were using the original SI/CI v_add_i32/v_sub_i32 names. Later targets reintroduced these names as carryless instructions with a saturating clamp bit, which we do not define. Do this rename so we can unambiguously add these missing instructions. The carry-in versions should also be renamed, but at least those had a consistent _u32 name to begin with. The 16-bit instructions were also renamed, but aren't ambiguous. This does regress assembler error message quality in some cases. In mismatched wave32/wave64 situations, this will switch from "unsupported instruction" to "invalid operand", with the error pointing at the wrong position. I couldn't quite follow how the assembler selects these, but the previous behavior seemed accidental to me. It looked like there was a partial attempt to handle this which was never completed (i.e. there is an AMDGPUOperand::isBoolReg but it isn't used for anything).
2020-07-14 21:18:36 +08:00
; GFX6: %ineg:vgpr_32, dead %4:sreg_64_xexec = V_SUB_CO_U32_e64 %zero, %src0, 0, implicit $exec
AMDGPU/GlobalISel: Fix import of s_abs_i32 pattern
2020-01-07 23:22:06 +08:00
; GFX6: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
; GFX6: S_ENDPGM 0, implicit %smax
; GFX9-LABEL: name: smax_neg_abs_pattern_s32_vv
; GFX9: liveins: $vgpr0
; GFX9: %src0:vgpr_32 = COPY $vgpr0
; GFX9: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX9: %ineg:vgpr_32 = V_SUB_U32_e64 %zero, %src0, 0, implicit $exec
; GFX9: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
; GFX9: S_ENDPGM 0, implicit %smax
%src0:vgpr(s32) = COPY $vgpr0
%zero:vgpr(s32) = G_CONSTANT i32 0
%ineg:vgpr(s32) = G_SUB %zero, %src0
%smax:vgpr(s32) = G_SMAX %src0, %ineg
S_ENDPGM 0, implicit %smax
...
# FIXME: Violates constant bus restriction
# ---
# name: smax_neg_abs_pattern_s32_vs
# legalized: true
# regBankSelected: true
# body: |
# bb.0:
# liveins: $sgpr0
# %src0:sgpr(s32) = COPY $sgpr0
# %zero:sgpr(s32) = G_CONSTANT i32 0
# %ineg:sgpr(s32) = G_SUB %zero, %src0
# %smax:vgpr(s32) = G_SMAX %src0, %ineg
# S_ENDPGM 0, implicit %smax
# ...