2007-01-19 15:51:42 +08:00
|
|
|
//===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-30 04:36:04 +08:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2007-01-19 15:51:42 +08:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file describes the ARM VP instruction set.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// ARM VFP Instruction templates.
|
|
|
|
//
|
|
|
|
|
|
|
|
// ARM Float Instruction
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class ASI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
|
2007-08-07 09:37:15 +08:00
|
|
|
: AI<0x0, outs, ins, VFPFrm, opc, asm, pattern> {
|
2007-01-19 15:51:42 +08:00
|
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class ASI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
|
2007-08-07 09:37:15 +08:00
|
|
|
: I<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
|
|
|
|
VFPFrm, opc, asm, "", pattern> {
|
2007-01-19 15:51:42 +08:00
|
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
|
|
}
|
|
|
|
|
|
|
|
// ARM Double Instruction
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class ADI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
|
2007-08-07 09:37:15 +08:00
|
|
|
: AI<0x0, outs, ins, VFPFrm, opc, asm, pattern> {
|
2007-01-19 15:51:42 +08:00
|
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class ADI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
|
2007-08-07 09:37:15 +08:00
|
|
|
: I<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
|
|
|
|
VFPFrm, opc, asm, "", pattern> {
|
2007-01-19 15:51:42 +08:00
|
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
|
|
}
|
|
|
|
|
2007-05-15 09:29:07 +08:00
|
|
|
// Special cases.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class AXSI<dag outs, dag ins, string asm, list<dag> pattern>
|
2007-08-07 09:37:15 +08:00
|
|
|
: XI<0x0, outs, ins, AddrModeNone, Size4Bytes, IndexModeNone,
|
|
|
|
VFPFrm, asm, "", pattern> {
|
2007-05-15 09:29:07 +08:00
|
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class AXSI5<dag outs, dag ins, string asm, list<dag> pattern>
|
2007-08-07 09:37:15 +08:00
|
|
|
: XI<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
|
|
|
|
VFPFrm, asm, "", pattern> {
|
2007-05-15 09:29:07 +08:00
|
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class AXDI<dag outs, dag ins, string asm, list<dag> pattern>
|
2007-08-07 09:37:15 +08:00
|
|
|
: XI<0x0, outs, ins, AddrModeNone, Size4Bytes, IndexModeNone,
|
|
|
|
VFPFrm, asm, "", pattern> {
|
2007-05-15 09:29:07 +08:00
|
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class AXDI5<dag outs, dag ins, string asm, list<dag> pattern>
|
2007-08-07 09:37:15 +08:00
|
|
|
: XI<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
|
|
|
|
VFPFrm, asm, "", pattern> {
|
2007-05-15 09:29:07 +08:00
|
|
|
// TODO: Mark the instructions with the appropriate subtarget info.
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-01-19 15:51:42 +08:00
|
|
|
def SDT_FTOI :
|
|
|
|
SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
|
|
|
|
def SDT_ITOF :
|
|
|
|
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
|
|
|
|
def SDT_CMPFP0 :
|
|
|
|
SDTypeProfile<0, 1, [SDTCisFP<0>]>;
|
|
|
|
def SDT_FMDRR :
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
|
|
|
|
SDTCisSameAs<1, 2>]>;
|
|
|
|
|
|
|
|
def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
|
|
|
|
def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
|
|
|
|
def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
|
|
|
|
def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
|
|
|
|
def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTRet, [SDNPInFlag,SDNPOutFlag]>;
|
|
|
|
def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
|
|
|
|
def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
|
|
|
|
def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Load / store Instructions.
|
|
|
|
//
|
|
|
|
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fldd", " $dst, $addr",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (load addrmode5:$addr))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FLDS : ASI5<(outs SPR:$dst), (ins addrmode5:$addr),
|
2007-05-15 09:29:07 +08:00
|
|
|
"flds", " $dst, $addr",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (load addrmode5:$addr))]>;
|
2008-01-07 07:38:27 +08:00
|
|
|
} // isSimpleLoad
|
2007-01-19 15:51:42 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fstd", " $src, $addr",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(store DPR:$src, addrmode5:$addr)]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fsts", " $src, $addr",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(store SPR:$src, addrmode5:$addr)]>;
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Load / store multiple Instructions.
|
|
|
|
//
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
|
|
|
|
variable_ops),
|
2007-05-30 07:34:19 +08:00
|
|
|
"fldm${addr:submode}d${p} ${addr:base}, $dst1",
|
2007-05-15 09:29:07 +08:00
|
|
|
[]>;
|
2007-01-19 15:51:42 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
|
|
|
|
variable_ops),
|
2007-05-30 07:34:19 +08:00
|
|
|
"fldm${addr:submode}s${p} ${addr:base}, $dst1",
|
2007-05-15 09:29:07 +08:00
|
|
|
[]>;
|
2007-01-19 15:51:42 +08:00
|
|
|
|
2008-01-06 16:36:04 +08:00
|
|
|
let mayStore = 1 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
|
|
|
|
variable_ops),
|
2007-05-30 07:34:19 +08:00
|
|
|
"fstm${addr:submode}d${p} ${addr:base}, $src1",
|
2007-01-19 15:51:42 +08:00
|
|
|
[]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
|
|
|
|
variable_ops),
|
2007-05-30 07:34:19 +08:00
|
|
|
"fstm${addr:submode}s${p} ${addr:base}, $src1",
|
2007-01-19 15:51:42 +08:00
|
|
|
[]>;
|
2008-01-06 16:36:04 +08:00
|
|
|
} // mayStore
|
2007-01-19 15:51:42 +08:00
|
|
|
|
|
|
|
// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FP Binary Operations.
|
|
|
|
//
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FADDD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"faddd", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FADDS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fadds", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FCMPED : ADI<(outs), (ins DPR:$a, DPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fcmped", " $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(arm_cmpfp DPR:$a, DPR:$b)]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FCMPES : ASI<(outs), (ins SPR:$a, SPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fcmpes", " $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(arm_cmpfp SPR:$a, SPR:$b)]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FDIVD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fdivd", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FDIVS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fdivs", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FMULD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fmuld", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FMULS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fmuls", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
|
2007-05-03 08:32:00 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FNMULD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fnmuld", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FNMULS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fnmuls", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
|
|
|
|
|
2007-05-03 08:32:00 +08:00
|
|
|
// Match reassociated forms only if not sign dependent rounding.
|
|
|
|
def : Pat<(fmul (fneg DPR:$a), DPR:$b),
|
|
|
|
(FNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
|
|
|
|
def : Pat<(fmul (fneg SPR:$a), SPR:$b),
|
|
|
|
(FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
|
|
|
|
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FSUBD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fsubd", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FSUBS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fsubs", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FP Unary Operations.
|
|
|
|
//
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FABSD : ADI<(outs DPR:$dst), (ins DPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fabsd", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fabs DPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FABSS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fabss", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fabs SPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FCMPEZD : ADI<(outs), (ins DPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fcmpezd", " $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(arm_cmpfp0 DPR:$a)]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FCMPEZS : ASI<(outs), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fcmpezs", " $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(arm_cmpfp0 SPR:$a)]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FCVTDS : ADI<(outs DPR:$dst), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fcvtds", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fextend SPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FCVTSD : ADI<(outs SPR:$dst), (ins DPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fcvtsd", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fround DPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FCPYD : ADI<(outs DPR:$dst), (ins DPR:$a),
|
2007-07-05 15:13:32 +08:00
|
|
|
"fcpyd", " $dst, $a", []>;
|
2007-01-19 15:51:42 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FCPYS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
2007-07-05 15:13:32 +08:00
|
|
|
"fcpys", " $dst, $a", []>;
|
2007-01-19 15:51:42 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FNEGD : ADI<(outs DPR:$dst), (ins DPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fnegd", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fneg DPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FNEGS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fnegs", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fneg SPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FSQRTD : ADI<(outs DPR:$dst), (ins DPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fsqrtd", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fsqrt DPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FSQRTS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fsqrts", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fsqrt SPR:$a))]>;
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FP <-> GPR Copies. Int <-> FP Conversions.
|
|
|
|
//
|
|
|
|
|
2007-12-13 07:12:09 +08:00
|
|
|
let isImplicitDef = 1 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def IMPLICIT_DEF_SPR : PseudoInst<(outs SPR:$rD), (ins pred:$p),
|
2007-01-19 15:51:42 +08:00
|
|
|
"@ IMPLICIT_DEF_SPR $rD",
|
|
|
|
[(set SPR:$rD, (undef))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def IMPLICIT_DEF_DPR : PseudoInst<(outs DPR:$rD), (ins pred:$p),
|
2007-01-19 15:51:42 +08:00
|
|
|
"@ IMPLICIT_DEF_DPR $rD",
|
|
|
|
[(set DPR:$rD, (undef))]>;
|
2007-12-13 07:12:09 +08:00
|
|
|
}
|
2007-01-19 15:51:42 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FMRS : ASI<(outs GPR:$dst), (ins SPR:$src),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fmrs", " $dst, $src",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set GPR:$dst, (bitconvert SPR:$src))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FMSR : ASI<(outs SPR:$dst), (ins GPR:$src),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fmsr", " $dst, $src",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (bitconvert GPR:$src))]>;
|
|
|
|
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FMRRD : ADI<(outs GPR:$dst1, GPR:$dst2), (ins DPR:$src),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fmrrd", " $dst1, $dst2, $src",
|
2007-01-19 15:51:42 +08:00
|
|
|
[/* FIXME: Can't write pattern for multiple result instr*/]>;
|
|
|
|
|
|
|
|
// FMDHR: GPR -> SPR
|
|
|
|
// FMDLR: GPR -> SPR
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FMDRR : ADI<(outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fmdrr", " $dst, $src1, $src2",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
|
|
|
|
|
|
|
|
// FMRDH: SPR -> GPR
|
|
|
|
// FMRDL: SPR -> GPR
|
|
|
|
// FMRRS: SPR -> GPR
|
|
|
|
// FMRX : SPR system reg -> GPR
|
|
|
|
|
|
|
|
// FMSRR: GPR -> SPR
|
|
|
|
|
2007-09-12 03:55:27 +08:00
|
|
|
let Defs = [CPSR] in
|
|
|
|
def FMSTAT : ASI<(outs), (ins), "fmstat", "", [(arm_fmstat)]>;
|
2007-01-19 15:51:42 +08:00
|
|
|
|
|
|
|
// FMXR: GPR -> VFP Sstem reg
|
|
|
|
|
|
|
|
|
|
|
|
// Int to FP:
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FSITOD : ADI<(outs DPR:$dst), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fsitod", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (arm_sitof SPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FSITOS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fsitos", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (arm_sitof SPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FUITOD : ADI<(outs DPR:$dst), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fuitod", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (arm_uitof SPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FUITOS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fuitos", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (arm_uitof SPR:$a))]>;
|
|
|
|
|
|
|
|
// FP to Int:
|
|
|
|
// Always set Z bit in the instruction, i.e. "round towards zero" variants.
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FTOSIZD : ADI<(outs SPR:$dst), (ins DPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"ftosizd", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (arm_ftosi DPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FTOSIZS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"ftosizs", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (arm_ftosi SPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FTOUIZD : ADI<(outs SPR:$dst), (ins DPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"ftouizd", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (arm_ftoui DPR:$a))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FTOUIZS : ASI<(outs SPR:$dst), (ins SPR:$a),
|
2007-05-15 09:29:07 +08:00
|
|
|
"ftouizs", " $dst, $a",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (arm_ftoui SPR:$a))]>;
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FP FMA Operations.
|
|
|
|
//
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FMACD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fmacd", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FMACS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fmacs", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FMSCD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fmscd", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FMSCS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fmscs", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FNMACD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fnmacd", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FNMACS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fnmacs", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FNMSCD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fnmscd", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FNMSCS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
2007-05-15 09:29:07 +08:00
|
|
|
"fnmscs", " $dst, $a, $b",
|
2007-01-19 15:51:42 +08:00
|
|
|
[(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FP Conditional moves.
|
|
|
|
//
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FCPYDcc : ADI<(outs DPR:$dst), (ins DPR:$false, DPR:$true),
|
2007-07-07 07:34:09 +08:00
|
|
|
"fcpyd", " $dst, $true",
|
2007-07-05 15:13:32 +08:00
|
|
|
[/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
|
|
|
|
RegConstraint<"$false = $dst">;
|
2007-01-19 15:51:42 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FCPYScc : ASI<(outs SPR:$dst), (ins SPR:$false, SPR:$true),
|
2007-07-07 07:34:09 +08:00
|
|
|
"fcpys", " $dst, $true",
|
2007-07-05 15:13:32 +08:00
|
|
|
[/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
|
|
|
|
RegConstraint<"$false = $dst">;
|
2007-01-19 15:51:42 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FNEGDcc : ADI<(outs DPR:$dst), (ins DPR:$false, DPR:$true),
|
2007-07-07 07:34:09 +08:00
|
|
|
"fnegd", " $dst, $true",
|
2007-07-05 15:13:32 +08:00
|
|
|
[/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
|
|
|
|
RegConstraint<"$false = $dst">;
|
2007-01-19 15:51:42 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FNEGScc : ASI<(outs SPR:$dst), (ins SPR:$false, SPR:$true),
|
2007-07-07 07:34:09 +08:00
|
|
|
"fnegs", " $dst, $true",
|
2007-07-05 15:13:32 +08:00
|
|
|
[/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
|
|
|
|
RegConstraint<"$false = $dst">;
|