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llvm-project/llvm/test/MC/ARM/invalid-fp-armv8.s

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Add subtarget feature support for Cortex-A53 Some previous implicit defaults have changed, for example FP and NEON are now on by default. llvm-svn: 192590
2013-10-14 21:16:57 +08:00
@ RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=V8
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision. llvm-svn: 185620
2013-07-04 18:04:08 +08:00
@ VCVT{B,T}
vcvtt.f64.f16 d3, s1
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
@ V7-NOT: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee]
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision. llvm-svn: 185620
2013-07-04 18:04:08 +08:00
vcvtt.f16.f64 s5, d12
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
@ V7-NOT: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee]
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision. llvm-svn: 185620
2013-07-04 18:04:08 +08:00
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vsel.f32 s3, s4, s6
@ V8: error: invalid instruction
vselne.f32 s3, s4, s6
@ V8: error: invalid instruction
vselmi.f32 s3, s4, s6
@ V8: error: invalid instruction
vselpl.f32 s3, s4, s6
@ V8: error: invalid instruction
vselvc.f32 s3, s4, s6
@ V8: error: invalid instruction
vselcs.f32 s3, s4, s6
@ V8: error: invalid instruction
vselcc.f32 s3, s4, s6
@ V8: error: invalid instruction
vselhs.f32 s3, s4, s6
@ V8: error: invalid instruction
vsello.f32 s3, s4, s6
@ V8: error: invalid instruction
vselhi.f32 s3, s4, s6
@ V8: error: invalid instruction
vsells.f32 s3, s4, s6
@ V8: error: invalid instruction
vsellt.f32 s3, s4, s6
@ V8: error: invalid instruction
vselle.f32 s3, s4, s6
@ V8: error: invalid instruction
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision. llvm-svn: 185620
2013-07-04 18:04:08 +08:00
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vseleq.f32 s0, d2, d1
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vselgt.f64 s3, s2, s1
@ V8: error: invalid operand for instruction
vselgt.f32 s0, q3, q1
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vselgt.f64 q0, s3, q1
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vmaxnm.f32 s0, d2, d1
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vminnm.f64 s3, s2, s1
@ V8: error: invalid operand for instruction
vmaxnm.f32 s0, q3, q1
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vmaxnm.f64 q0, s3, q1
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vmaxnmgt.f64 q0, s3, q1
@ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
vcvta.s32.f64 d3, s2
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vcvtp.s32.f32 d3, s2
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ V8: error: operand must be a register in range [s0, s31]
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vcvtn.u32.f64 d3, s2
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vcvtm.u32.f32 d3, s2
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ V8: error: operand must be a register in range [s0, s31]
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vcvtnge.u32.f64 d3, s2
@ V8: error: instruction 'vcvtn' is not predicable, but condition code specified
vcvtbgt.f64.f16 q0, d3
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vcvttlt.f64.f16 s0, s3
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ V8: error: invalid instruction, any one of the following would fix this:
@ V8: note: operand must be a register in range [d0, d31]
[ARM] Use new assembler diags for ARM This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
2017-10-03 18:26:11 +08:00
@ V8: note: invalid operand for instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vcvttvs.f16.f64 s0, s3
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ V8: error: invalid instruction, any one of the following would fix this:
@ V8: note: operand must be a register in range [d0, d31]
[ARM] Use new assembler diags for ARM This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
2017-10-03 18:26:11 +08:00
@ V8: note: invalid operand for instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vcvtthi.f16.f64 q0, d3
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ V8: error: operand must be a register in range [s0, s31]
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vrintrlo.f32.f32 d3, q0
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vrintxcs.f32.f32 d3, d0
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vrinta.f64.f64 s3, q0
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ V8: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vrintn.f32.f32 d3, d0
@ V8: error: instruction requires: NEON
vrintp.f32 q3, q0
@ V8: error: instruction requires: NEON
vrintmlt.f32 q3, q0
@ V8: error: instruction 'vrintm' is not predicable, but condition code specified