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llvm-project/llvm/test/CodeGen/X86/vec_insert-7.ll

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[X86][MMX] Regenerated vector insertion test. Shows the true horror of what is going on.... llvm-svn: 256713
2016-01-04 03:17:37 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X64
[X86][MMX] Regenerated vector insertion test. Shows the true horror of what is going on.... llvm-svn: 256713
2016-01-04 03:17:37 +08:00
[CodeGen] Print register names in lowercase in both MIR and debug output As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
2017-11-29 01:15:09 +08:00
; MMX insertelement is not available; these are promoted to xmm.
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 07:57:10 +08:00
; (Without SSE they are split to two ints, and the code is much better.)
Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code. Also commit Mon Ping's VSETCC patch llvm-svn: 54039
2008-07-26 03:05:58 +08:00
[X86][MMX] Regenerated vector insertion test. Shows the true horror of what is going on.... llvm-svn: 256713
2016-01-04 03:17:37 +08:00
define x86_mmx @mmx_movzl(x86_mmx %x) nounwind {
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X32-LABEL: mmx_movzl:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X32: ## %bb.0:
[X86] Add custom type legalization for v2i32/v4i16/v8i8->mmx bitcasts to avoid a store/load to/from the stack. Widen the input to a 128 bit vector by padding with undef elements. Then use a movdq2q to convert from xmm register to mmx register. llvm-svn: 348086
2018-12-02 13:46:50 +08:00
; X32-NEXT: subl $12, %esp
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X32-NEXT: movl $32, %eax
[SelectionDAG] SimplifyDemandedVectorElts - add support for VECTOR_INSERT_ELT Differential Revision: https://reviews.llvm.org/D43431 llvm-svn: 325449
2018-02-18 05:49:40 +08:00
; X32-NEXT: movd %eax, %xmm0
[X86] Add custom type legalization for v2i32/v4i16/v8i8->mmx bitcasts to avoid a store/load to/from the stack. Widen the input to a 128 bit vector by padding with undef elements. Then use a movdq2q to convert from xmm register to mmx register. llvm-svn: 348086
2018-12-02 13:46:50 +08:00
; X32-NEXT: movdq2q %xmm0, %mm0
; X32-NEXT: addl $12, %esp
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X32-NEXT: retl
;
; X64-LABEL: mmx_movzl:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: ## %bb.0:
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X64-NEXT: movl $32, %eax
[X86] Custom type legalize v2i32/v4i16/v8i8->i64 bitcasts in 64-bit mode similar to what's done when the destination is f64. The generic legalizer will fall back to a stack spill that uses a truncating store. That store will get expanded into a shuffle and non-truncating store on pre-avx512 targets. Once that happens the stack store/load pair will be combined away leaving behind the shuffle and bitcasts. On avx512 targets the truncating store is legal so doesn't get folded away. By custom legalizing it we can avoid this churn and maybe produce better code. llvm-svn: 348085
2018-12-02 13:46:48 +08:00
; X64-NEXT: movd %eax, %xmm0
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X64-NEXT: retq
[X86][MMX] Regenerated vector insertion test. Shows the true horror of what is going on.... llvm-svn: 256713
2016-01-04 03:17:37 +08:00
%tmp = bitcast x86_mmx %x to <2 x i32>
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
%tmp3 = insertelement <2 x i32> %tmp, i32 32, i32 0
%tmp8 = insertelement <2 x i32> %tmp3, i32 0, i32 1
[X86][MMX] Regenerated vector insertion test. Shows the true horror of what is going on.... llvm-svn: 256713
2016-01-04 03:17:37 +08:00
%tmp9 = bitcast <2 x i32> %tmp8 to x86_mmx
ret x86_mmx %tmp9
Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code. Also commit Mon Ping's VSETCC patch llvm-svn: 54039
2008-07-26 03:05:58 +08:00
}