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llvm-project/llvm/test/MC/AArch64/neon-scalar-mul.s

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[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -show-encoding < %s | FileCheck %s
[AArch64] Add support for NEON scalar arithmetic instructions: SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. llvm-svn: 192107
2013-10-08 00:36:15 +08:00
// Check that the assembler can handle the documented syntax for AArch64
//----------------------------------------------------------------------
// Scalar Integer Saturating Doubling Multiply Half High
//----------------------------------------------------------------------
sqdmulh h10, h11, h12
sqdmulh s20, s21, s2
// CHECK: sqdmulh h10, h11, h12 // encoding: [0x6a,0xb5,0x6c,0x5e]
// CHECK: sqdmulh s20, s21, s2 // encoding: [0xb4,0xb6,0xa2,0x5e]
//----------------------------------------------------------------------
// Scalar Integer Saturating Rounding Doubling Multiply Half High
//----------------------------------------------------------------------
sqrdmulh h10, h11, h12
sqrdmulh s20, s21, s2
// CHECK: sqrdmulh h10, h11, h12 // encoding: [0x6a,0xb5,0x6c,0x7e]
// CHECK: sqrdmulh s20, s21, s2 // encoding: [0xb4,0xb6,0xa2,0x7e]
//----------------------------------------------------------------------
// Floating-point Multiply Extended
//----------------------------------------------------------------------
[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
fmulx h20, h22, h15
[AArch64] Add support for NEON scalar arithmetic instructions: SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. llvm-svn: 192107
2013-10-08 00:36:15 +08:00
fmulx s20, s22, s15
fmulx d23, d11, d1
[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
// CHECK: fmulx h20, h22, h15 // encoding: [0xd4,0x1e,0x4f,0x5e]
[AArch64] Add support for NEON scalar arithmetic instructions: SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. llvm-svn: 192107
2013-10-08 00:36:15 +08:00
// CHECK: fmulx s20, s22, s15 // encoding: [0xd4,0xde,0x2f,0x5e]
// CHECK: fmulx d23, d11, d1 // encoding: [0x77,0xdd,0x61,0x5e]
[AArch64] Add support for NEON scalar three register different instruction class. The instruction class includes the signed saturating doubling multiply-add long, signed saturating doubling multiply-subtract long, and the signed saturating doubling multiply long instructions. llvm-svn: 192908
2013-10-18 02:12:29 +08:00
//----------------------------------------------------------------------
// Signed Saturating Doubling Multiply-Add Long
//----------------------------------------------------------------------
sqdmlal s17, h27, h12
sqdmlal d19, s24, s12
// CHECK: sqdmlal s17, h27, h12 // encoding: [0x71,0x93,0x6c,0x5e]
// CHECK: sqdmlal d19, s24, s12 // encoding: [0x13,0x93,0xac,0x5e]
//----------------------------------------------------------------------
// Signed Saturating Doubling Multiply-Subtract Long
//----------------------------------------------------------------------
sqdmlsl s14, h12, h25
sqdmlsl d12, s23, s13
// CHECK: sqdmlsl s14, h12, h25 // encoding: [0x8e,0xb1,0x79,0x5e]
// CHECK: sqdmlsl d12, s23, s13 // encoding: [0xec,0xb2,0xad,0x5e]
//----------------------------------------------------------------------
// Signed Saturating Doubling Multiply Long
//----------------------------------------------------------------------
sqdmull s12, h22, h12
sqdmull d15, s22, s12
// CHECK: sqdmull s12, h22, h12 // encoding: [0xcc,0xd2,0x6c,0x5e]
// CHECK: sqdmull d15, s22, s12 // encoding: [0xcf,0xd2,0xac,0x5e]