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llvm-project/llvm/test/MC/AArch64/arm64-diags.s

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ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
foo:
; The first should encode as an expression. The second should error expecting
; a register.
ldr x3, (foo + 4)
ldr x3, [foo + 4]
; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58]
AArch64/ARM64: move ARM64 into AArch64's place This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
2014-05-24 20:50:23 +08:00
; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_aarch64_ldr_pcrel_imm19
Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand. Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. (Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win builder does not seem to rebuild AArch64GenAsmMatcher.inc with the newly built TableGen due to a missing dependency somewhere (see: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html)) Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 320711
2017-12-15 00:09:48 +08:00
; CHECK-ERRORS: error: invalid operand for instruction
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; The last argument should be flagged as an error. rdar://9576009
ld4.8b {v0, v1, v2, v3}, [x0], #33
; CHECK-ERRORS: error: invalid operand for instruction
; CHECK-ERRORS: ld4.8b {v0, v1, v2, v3}, [x0], #33
ldr x0, [x0, #804]
ldr w0, [x0, #802]
ldr x0, [x0, #804]!
ldr w0, [w0, #301]!
ldr x0, [x0], #804
ldr w0, [w0], #301
ldp w3, w4, [x5, #11]!
ldp x3, x4, [x5, #12]!
ldp q3, q4, [x5, #12]!
ldp w3, w4, [x5], #11
ldp x3, x4, [x5], #12
ldp q3, q4, [x5], #12
ldur x0, [x1, #-257]
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldr x0, [x0, #804]
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldr w0, [x0, #802]
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldr x0, [x0, #804]!
; CHECK-ERRORS: ^
Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand. Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. (Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win builder does not seem to rebuild AArch64GenAsmMatcher.inc with the newly built TableGen due to a missing dependency somewhere (see: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html)) Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 320711
2017-12-15 00:09:48 +08:00
; CHECK-ERRORS: error: invalid operand for instruction
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldr w0, [w0, #301]!
[ARM64] Improve load/store diagnostics and forbid 32-bit register addresses llvm-svn: 208864
2014-05-15 19:08:30 +08:00
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldr x0, [x0], #804
; CHECK-ERRORS: ^
Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand. Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. (Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win builder does not seem to rebuild AArch64GenAsmMatcher.inc with the newly built TableGen due to a missing dependency somewhere (see: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html)) Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 320711
2017-12-15 00:09:48 +08:00
; CHECK-ERRORS: error: invalid operand for instruction
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldr w0, [w0], #301
[ARM64] Improve load/store diagnostics and forbid 32-bit register addresses llvm-svn: 208864
2014-05-15 19:08:30 +08:00
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldp w3, w4, [x5, #11]!
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldp x3, x4, [x5, #12]!
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldp q3, q4, [x5, #12]!
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldp w3, w4, [x5], #11
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldp x3, x4, [x5], #12
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldp q3, q4, [x5], #12
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ldur x0, [x1, #-257]
; CHECK-ERRORS: ^
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
2014-05-13 15:35:12 +08:00
ldrb w1, [x3, w3, sxtw #4]
ldrh w1, [x3, w3, sxtw #4]
ldr w1, [x3, w3, sxtw #4]
ldr x1, [x3, w3, sxtw #4]
ldr b1, [x3, w3, sxtw #4]
ldr h1, [x3, w3, sxtw #4]
ldr s1, [x3, w3, sxtw #4]
ldr d1, [x3, w3, sxtw #4]
ldr q1, [x3, w3, sxtw #1]
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
2014-05-13 15:35:12 +08:00
; CHECK-ERRORS:ldrb w1, [x3, w3, sxtw #4]
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
2014-05-13 15:35:12 +08:00
; CHECK-ERRORS:ldrh w1, [x3, w3, sxtw #4]
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
2014-05-13 15:35:12 +08:00
; CHECK-ERRORS:ldr w1, [x3, w3, sxtw #4]
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
2014-05-13 15:35:12 +08:00
; CHECK-ERRORS:ldr x1, [x3, w3, sxtw #4]
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
2014-05-13 15:35:12 +08:00
; CHECK-ERRORS:ldr b1, [x3, w3, sxtw #4]
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
2014-05-13 15:35:12 +08:00
; CHECK-ERRORS:ldr h1, [x3, w3, sxtw #4]
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
2014-05-13 15:35:12 +08:00
; CHECK-ERRORS:ldr s1, [x3, w3, sxtw #4]
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
2014-05-13 15:35:12 +08:00
; CHECK-ERRORS:ldr d1, [x3, w3, sxtw #4]
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
2014-05-13 15:35:12 +08:00
; CHECK-ERRORS:ldr q1, [x3, w3, sxtw #1]
; CHECK-ERRORS: ^
ARM64: Improve diagnostics for malformed reg+reg addressing mode. Make sure only general purpose registers are valid for offset regs and that 32-bit regs are only valid for sxtw and uxtw extends. llvm-svn: 206799
2014-04-22 05:45:57 +08:00
; Check that register offset addressing modes only accept 32-bit offset
; registers when using uxtw/sxtw extends. Everything else requires a 64-bit
; register.
str d1, [x3, w3, sxtx #3]
ldr s1, [x3, d3, sxtx #2]
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
ARM64: Improve diagnostics for malformed reg+reg addressing mode. Make sure only general purpose registers are valid for offset regs and that 32-bit regs are only valid for sxtw and uxtw extends. llvm-svn: 206799
2014-04-22 05:45:57 +08:00
; CHECK-ERRORS: str d1, [x3, w3, sxtx #3]
; CHECK-ERRORS: ^
ARM64: separate load/store operands to simplify assembler This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
2014-05-22 19:56:09 +08:00
; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
ARM64: Improve diagnostics for malformed reg+reg addressing mode. Make sure only general purpose registers are valid for offset regs and that 32-bit regs are only valid for sxtw and uxtw extends. llvm-svn: 206799
2014-04-22 05:45:57 +08:00
; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2]
; CHECK-ERRORS: ^
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; Shift immediates range checking.
sqrshrn b4, h9, #10
rshrn v9.8b, v11.8h, #17
sqrshrn v7.4h, v8.4s, #39
uqshrn2 v4.4s, v5.2d, #67
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: sqrshrn b4, h9, #10
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: rshrn v9.8b, v11.8h, #17
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: immediate must be an integer in range [1, 16].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: sqrshrn v7.4h, v8.4s, #39
; CHECK-ERRORS: ^
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
; CHECK-ERRORS: error: immediate must be an integer in range [1, 32].
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: uqshrn2 v4.4s, v5.2d, #67
; CHECK-ERRORS: ^
st1.s4 {v14, v15}, [x2], #32
; CHECK-ERRORS: error: invalid type suffix for instruction
; CHECK-ERRORS: st1.s4 {v14, v15}, [x2], #32
; CHECK-ERRORS: ^
; Load pair instructions where Rt==Rt2 and writeback load/store instructions
; where Rt==Rn or Rt2==Rn are unpredicatable.
ldp x1, x2, [x2], #16
ldp x2, x2, [x2], #16
ldp w1, w2, [x2], #16
ldp w2, w2, [x2], #16
ldp x1, x1, [x2]
[AArch64] Add negative tests for the SIMD & FP LDP instructions. LDP is unpredictable if the registers in the pair are identical, these tests check that we don't assemble instructions like that and error out instead. llvm-svn: 213074
2014-07-16 00:33:24 +08:00
ldp s1, s1, [x1], #8
ldp s1, s1, [x1, #8]!
ldp s1, s1, [x1, #8]
ldp d1, d1, [x1], #16
ldp d1, d1, [x1, #16]!
ldp d1, d1, [x1, #16]
ldp q1, q1, [x1], #32
ldp q1, q1, [x1, #32]!
ldp q1, q1, [x1, #32]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
ldr x2, [x2], #8
ldr x2, [x2, #8]!
ldr w2, [x2], #8
ldr w2, [x2, #8]!
str x2, [x2], #8
str x2, [x2, #8]!
str w2, [x2], #8
str w2, [x2, #8]!
; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
; CHECK-ERRORS: ldp x1, x2, [x2], #16
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
; CHECK-ERRORS: ldp x2, x2, [x2], #16
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
; CHECK-ERRORS: ldp w1, w2, [x2], #16
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
; CHECK-ERRORS: ldp w2, w2, [x2], #16
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp x1, x1, [x2]
; CHECK-ERRORS: ^
[AArch64] Add negative tests for the SIMD & FP LDP instructions. LDP is unpredictable if the registers in the pair are identical, these tests check that we don't assemble instructions like that and error out instead. llvm-svn: 213074
2014-07-16 00:33:24 +08:00
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp s1, s1, [x1], #8
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp s1, s1, [x1, #8]!
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp s1, s1, [x1, #8]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp d1, d1, [x1], #16
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp d1, d1, [x1, #16]!
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp d1, d1, [x1, #16]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp q1, q1, [x1], #32
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp q1, q1, [x1, #32]!
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp q1, q1, [x1, #32]
; CHECK-ERRORS: ^
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
; CHECK-ERRORS: ldr x2, [x2], #8
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
; CHECK-ERRORS: ldr x2, [x2, #8]!
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
; CHECK-ERRORS: ldr w2, [x2], #8
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
; CHECK-ERRORS: ldr w2, [x2, #8]!
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
; CHECK-ERRORS: str x2, [x2], #8
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
; CHECK-ERRORS: str x2, [x2, #8]!
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
; CHECK-ERRORS: str w2, [x2], #8
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
; CHECK-ERRORS: str w2, [x2, #8]!
; CHECK-ERRORS: ^
AArch64: diagnose unpredictable store-exclusive instructions Much like any written register in load/store instructions, the status register is not allowed to overlap with any others. So diagnose it like we already do with the other cases. llvm-svn: 329687
2018-04-10 19:04:29 +08:00
; Store exclusive instructions are unpredictable if the status register clashes
; with anything.
stlxrb w1, w1, [x5]
stxrb w3, w5, [x3]
stxrh w7, w9, [x7]
stlxrh wzr, wzr, [x13]
stxr w9, w9, [x12]
stlxr w22, x1, [x22]
stxr w4, x4, [x9]
stlxr w5, x0, [x5]
; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
; CHECK-ERRORS: stlxrb w1, w1, [x5]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
; CHECK-ERRORS: stxrb w3, w5, [x3]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
; CHECK-ERRORS: stxrh w7, w9, [x7]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
; CHECK-ERRORS: stlxrh wzr, wzr, [x13]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
; CHECK-ERRORS: stxr w9, w9, [x12]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
; CHECK-ERRORS: stlxr w22, x1, [x22]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
; CHECK-ERRORS: stxr w4, x4, [x9]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
; CHECK-ERRORS: stlxr w5, x0, [x5]
; CHECK-ERRORS: ^
stxp w0, w0, w1, [x3]
stxp w0, w1, w0, [x5]
stxp w10, w4, w5, [x10]
stxp wzr, xzr, x4, [x5]
stxp w3, x5, x3, [sp]
stxp w25, x4, x2, [x25]
; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
; CHECK-ERRORS: stxp w0, w0, w1, [x3]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
; CHECK-ERRORS: stxp w0, w1, w0, [x5]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
; CHECK-ERRORS: stxp w10, w4, w5, [x10]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
; CHECK-ERRORS: stxp wzr, xzr, x4, [x5]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
; CHECK-ERRORS: stxp w3, x5, x3, [sp]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
; CHECK-ERRORS: stxp w25, x4, x2, [x25]
; CHECK-ERRORS: ^
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; The validity checking for shifted-immediate operands. rdar://13174476
; Where the immediate is out of range.
add w1, w2, w3, lsr #75
[ARM64] Correct more bounds checks/diagnostics for arithmetic shift operands llvm-svn: 208528
2014-05-12 17:41:43 +08:00
; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: add w1, w2, w3, lsr #75
; CHECK-ERRORS: ^
; logical instructions on 32-bit regs with shift > 31 is not legal
orr w0, w0, w0, lsl #32
[ARM64] Add proper bounds checking/diagnostics to logical shifts llvm-svn: 208540
2014-05-12 19:49:16 +08:00
; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: orr w0, w0, w0, lsl #32
; CHECK-ERRORS: ^
eor w0, w0, w0, lsl #32
[ARM64] Add proper bounds checking/diagnostics to logical shifts llvm-svn: 208540
2014-05-12 19:49:16 +08:00
; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: eor w0, w0, w0, lsl #32
; CHECK-ERRORS: ^
and w0, w0, w0, lsl #32
[ARM64] Add proper bounds checking/diagnostics to logical shifts llvm-svn: 208540
2014-05-12 19:49:16 +08:00
; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: and w0, w0, w0, lsl #32
; CHECK-ERRORS: ^
ands w0, w0, w0, lsl #32
[ARM64] Add proper bounds checking/diagnostics to logical shifts llvm-svn: 208540
2014-05-12 19:49:16 +08:00
; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK-ERRORS: ands w0, w0, w0, lsl #32
; CHECK-ERRORS: ^
; Relocated expressions should not be accepted for 32-bit adds or sub (imm)
add w3, w5, sym@PAGEOFF
; CHECK-ERRORS: error: invalid immediate expression
; CHECK-ERRORS: add w3, w5, sym@PAGEOFF
; CHECK-ERRORS: ^
adds w3, w5, sym@PAGEOFF
adds x9, x12, sym@PAGEOFF
; CHECK-ERRORS: error: invalid immediate expression
; CHECK-ERRORS: adds w3, w5, sym@PAGEOFF
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: invalid immediate expression
; CHECK-ERRORS: adds x9, x12, sym@PAGEOFF
; CHECK-ERRORS: ^
sub x3, x5, sym@PAGEOFF
sub w20, w30, sym@PAGEOFF
; CHECK-ERRORS: error: invalid immediate expression
; CHECK-ERRORS: sub x3, x5, sym@PAGEOFF
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: invalid immediate expression
; CHECK-ERRORS: sub w20, w30, sym@PAGEOFF
; CHECK-ERRORS: ^
subs w9, w10, sym@PAGEOFF
subs x20, x30, sym@PAGEOFF
; CHECK-ERRORS: error: invalid immediate expression
; CHECK-ERRORS: subs w9, w10, sym@PAGEOFF
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: invalid immediate expression
; CHECK-ERRORS: subs x20, x30, sym@PAGEOFF
; CHECK-ERRORS: ^
tbl v0.8b, { v1 }, v0.8b
tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
tbx v2.8b, { v0 }, v6.8b
; CHECK-ERRORS: error: invalid operand for instruction
; CHECK-ERRORS: tbl v0.8b, { v1 }, v0.8b
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: invalid operand for instruction
; CHECK-ERRORS: tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: invalid operand for instruction
; CHECK-ERRORS: tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: invalid operand for instruction
; CHECK-ERRORS: tbx v2.8b, { v0 }, v6.8b
; CHECK-ERRORS: ^
b.c #0x4
; CHECK-ERRORS: error: invalid condition code
; CHECK-ERRORS: b.c #0x4
; CHECK-ERRORS: ^
[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases. llvm-svn: 205876
2014-04-09 22:43:11 +08:00
ic ialluis, x0
; CHECK-ERRORS: error: specified ic op does not use a register
ic iallu, x0
; CHECK-ERRORS: error: specified ic op does not use a register
ic ivau
; CHECK-ERRORS: error: specified ic op requires a register
dc zva
; CHECK-ERRORS: error: specified dc op requires a register
dc ivac
; CHECK-ERRORS: error: specified dc op requires a register
dc isw
; CHECK-ERRORS: error: specified dc op requires a register
dc cvac
; CHECK-ERRORS: error: specified dc op requires a register
dc csw
; CHECK-ERRORS: error: specified dc op requires a register
dc cvau
; CHECK-ERRORS: error: specified dc op requires a register
dc civac
; CHECK-ERRORS: error: specified dc op requires a register
dc cisw
; CHECK-ERRORS: error: specified dc op requires a register
at s1e1r
; CHECK-ERRORS: error: specified at op requires a register
at s1e2r
; CHECK-ERRORS: error: specified at op requires a register
at s1e3r
; CHECK-ERRORS: error: specified at op requires a register
at s1e1w
; CHECK-ERRORS: error: specified at op requires a register
at s1e2w
; CHECK-ERRORS: error: specified at op requires a register
at s1e3w
; CHECK-ERRORS: error: specified at op requires a register
at s1e0r
; CHECK-ERRORS: error: specified at op requires a register
at s1e0w
; CHECK-ERRORS: error: specified at op requires a register
at s12e1r
; CHECK-ERRORS: error: specified at op requires a register
at s12e1w
; CHECK-ERRORS: error: specified at op requires a register
at s12e0r
; CHECK-ERRORS: error: specified at op requires a register
at s12e0w
; CHECK-ERRORS: error: specified at op requires a register
tlbi vmalle1is, x0
; CHECK-ERRORS: error: specified tlbi op does not use a register
tlbi vmalle1, x0
; CHECK-ERRORS: error: specified tlbi op does not use a register
tlbi alle1is, x0
; CHECK-ERRORS: error: specified tlbi op does not use a register
tlbi alle2is, x0
; CHECK-ERRORS: error: specified tlbi op does not use a register
tlbi alle3is, x0
; CHECK-ERRORS: error: specified tlbi op does not use a register
tlbi alle1, x0
; CHECK-ERRORS: error: specified tlbi op does not use a register
tlbi alle2, x0
; CHECK-ERRORS: error: specified tlbi op does not use a register
tlbi alle3, x0
; CHECK-ERRORS: error: specified tlbi op does not use a register
tlbi vae1is
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vae2is
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vae3is
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi aside1is
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vaae1is
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vale1is
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vaale1is
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vale2is
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vale3is
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vae1
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vae2
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vae3
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi aside1
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vaae1
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vale1
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vale2
; CHECK-ERRORS: error: specified tlbi op requires a register
tlbi vale3
; CHECK-ERRORS: error: specified tlbi op requires a register
[AArch64] Provide "too few operands" diags on short-form NEON also. We used to just say "invalid type suffix for instruction", which is misleading. This is because we fallback to the long-form matcher if the short-form matcher failed, losing the error information on the way. Save it, so that we can provide a little better diagnostics when the long-form matcher thinks a suffix is the cause of the error. llvm-svn: 244955
2015-08-14 05:09:13 +08:00
; Check that we give the proper "too few operands" diagnostic even when
; using short-form NEON.
add.16b v0, v1, v2, v3
add.8b v0, v1
sub.8h v0, v1
fadd.4s v0
fmul.2s
; CHECK-ERRORS: error: invalid operand for instruction
; CHECK-ERRORS: add.16b v0, v1, v2, v3
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: too few operands for instruction
; CHECK-ERRORS: add.8b v0, v1
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: too few operands for instruction
; CHECK-ERRORS: sub.8h v0, v1
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: too few operands for instruction
; CHECK-ERRORS: fadd.4s v0
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: too few operands for instruction
; CHECK-ERRORS: fmul.2s
; CHECK-ERRORS: ^
; Also for 2-operand instructions.
frsqrte.4s v0, v1, v2
frsqrte.2s v0
frecpe.2d
; CHECK-ERRORS: error: invalid operand for instruction
; CHECK-ERRORS: frsqrte.4s v0, v1, v2
Fix CHECK directives that weren't checking. llvm-svn: 246485
2015-09-01 05:10:35 +08:00
; CHECK-ERRORS: ^
[AArch64] Provide "too few operands" diags on short-form NEON also. We used to just say "invalid type suffix for instruction", which is misleading. This is because we fallback to the long-form matcher if the short-form matcher failed, losing the error information on the way. Save it, so that we can provide a little better diagnostics when the long-form matcher thinks a suffix is the cause of the error. llvm-svn: 244955
2015-08-14 05:09:13 +08:00
; CHECK-ERRORS: error: too few operands for instruction
; CHECK-ERRORS: frsqrte.2s v0
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: too few operands for instruction
; CHECK-ERRORS: frecpe.2d
; CHECK-ERRORS: ^
; And check that we do the same for non-NEON instructions.
b.ne
b.eq 0, 0
; CHECK-ERRORS: error: too few operands for instruction
; CHECK-ERRORS: b.ne
; CHECK-ERRORS: ^
Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand. Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. (Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win builder does not seem to rebuild AArch64GenAsmMatcher.inc with the newly built TableGen due to a missing dependency somewhere (see: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html)) Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 320711
2017-12-15 00:09:48 +08:00
; CHECK-ERRORS: error: invalid operand for instruction
[AArch64] Provide "too few operands" diags on short-form NEON also. We used to just say "invalid type suffix for instruction", which is misleading. This is because we fallback to the long-form matcher if the short-form matcher failed, losing the error information on the way. Save it, so that we can provide a little better diagnostics when the long-form matcher thinks a suffix is the cause of the error. llvm-svn: 244955
2015-08-14 05:09:13 +08:00
; CHECK-ERRORS: b.eq 0, 0
; CHECK-ERRORS: ^
[AArch64] Check the size of the vector before accessing its elements. This fixes an assert in AArch64AsmParser::MatchAndEmitInstruction. rdar://problem/23081753 llvm-svn: 250207
2015-10-14 02:55:34 +08:00
; Check that we give the proper "too few operands" diagnostic instead of
; asserting.
ldr
; CHECK-ERRORS: error: too few operands for instruction
; CHECK-ERRORS: ldr
; CHECK-ERRORS: ^