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llvm-project/llvm/test/CodeGen/Hexagon/vaddh.ll

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Enable all Hexagon tests. llvm-svn: 156824
2012-05-16 00:13:12 +08:00
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
; CHECK: vaddh(r{{[0-9]+}}, r{{[0-9]+}})
@j = external global i32
@k = external global i32
define void @foo() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* @j, align 4
%1 = load i32, i32* @k, align 4
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
%2 = call i32 @llvm.hexagon.A2.svaddh(i32 %0, i32 %1)
store i32 %2, i32* @k, align 4
ret void
}
declare i32 @llvm.hexagon.A2.svaddh(i32, i32) nounwind readnone