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llvm-project/llvm/test/MC/Mips/sext_64_32.ll

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[mips] Remove CPU-only triples from llvm-objdump commands. Summary: They aren't necessary since llvm-objdump can auto-detect the architecture. Reviewers: sdardis Subscribers: jfb, dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20904 llvm-svn: 271653
2016-06-03 18:22:22 +08:00
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \
; RUN: llvm-objdump -disassemble - | FileCheck %s
The define for 64 bit sign extension neglected to initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop llvm-svn: 161377
2012-08-07 08:35:22 +08:00
; Sign extend from 32 to 64 was creating nonsense opcodes
[mips] Stop reserving register AT and use register scavenger when a scratch register is needed. llvm-svn: 167341
2012-11-03 08:05:43 +08:00
; CHECK: sll ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
The define for 64 bit sign extension neglected to initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop llvm-svn: 161377
2012-08-07 08:35:22 +08:00
define i64 @foo(i32 %ival) nounwind readnone {
entry:
%conv = sext i32 %ival to i64
ret i64 %conv
}
Another 32 to 64 bit sign extension bug. The fields in the td definition were switched. llvm-svn: 161607
2012-08-10 03:43:18 +08:00
[mips] Stop reserving register AT and use register scavenger when a scratch register is needed. llvm-svn: 167341
2012-11-03 08:05:43 +08:00
; CHECK: dsll32 ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
Another 32 to 64 bit sign extension bug. The fields in the td definition were switched. llvm-svn: 161607
2012-08-10 03:43:18 +08:00
define i64 @foo_2(i32 %ival_2) nounwind readnone {
entry:
%conv_2 = zext i32 %ival_2 to i64
ret i64 %conv_2
}