llvm-project/llvm/test/MC/Mips/mips1/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding.
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | not FileCheck %s
# CHECK-NOT: encoding
# XFAIL: *

        .set noat
        lwc0    c0_entrylo,-7321($s2)
        swc0    c0_prid,18904($s3)
[mips] Added a full set of instruction test cases for all ISA's (but not ASE's). Summary: Where those ISA's are not currently supported, the test is run with the smallest superset of that ISA. Some instructions are valid but don't pass yet. These have been placed in the valid-xfail.s's which will XPASS if _any_ instruction starts working. The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3214 llvm-svn: 205180 2014-03-31 20:13:12 +08:00			`# Instructions that should be valid but currently fail for known reasons (e.g.`
			`# they aren't implemented yet).`
			`# This test is set up to XPASS if any instruction generates an encoding.`
			`#`
[mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V Summary: These processors will only be available for the integrated assembler at first (CodeGen will emit a fatal error saying they are not implemented). The intention is to work through the existing instructions and correctly annotate the ISA they were added in so that we have a sufficiently good base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain instructions and I believe it is best to define ISA's using set-union's as far as possible rather than using set-subtraction. Reviewers: vmedic Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D3569 llvm-svn: 208221 2014-05-08 00:25:22 +08:00			`# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \| not FileCheck %s`
[mips] Added a full set of instruction test cases for all ISA's (but not ASE's). Summary: Where those ISA's are not currently supported, the test is run with the smallest superset of that ISA. Some instructions are valid but don't pass yet. These have been placed in the valid-xfail.s's which will XPASS if _any_ instruction starts working. The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3214 llvm-svn: 205180 2014-03-31 20:13:12 +08:00			`# CHECK-NOT: encoding`
			`# XFAIL: *`

[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327 2014-05-08 23:17:29 +08:00			`.set noat`
			`lwc0 c0_entrylo,-7321($s2)`
			`swc0 c0_prid,18904($s3)`