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llvm-project/llvm/test/MC/Mips/macro-divu.s

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[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \
# RUN: FileCheck %s --check-prefix=CHECK-NOTRAP
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 \
# RUN: -mattr=+use-tcc-in-div | FileCheck %s --check-prefix=CHECK-TRAP
divu $25,$11
# CHECK-NOTRAP: bnez $11, 8 # encoding: [0x15,0x60,0x00,0x02]
# CHECK-NOTRAP: divu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1b]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
divu $24,$12
# CHECK-NOTRAP: bnez $12, 8 # encoding: [0x15,0x80,0x00,0x02]
# CHECK-NOTRAP: divu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1b]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
divu $25,$0
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
# CHECK-NOTRAP: divu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1b]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
divu $0,$9
# CHECK-NOTRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
divu $0,$0
# CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
divu $4,$5,$6
# CHECK-NOTRAP: bnez $6, 8 # encoding: [0x14,0xc0,0x00,0x02]
# CHECK-NOTRAP: divu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1b]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
divu $4,$5,$0
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
# CHECK-NOTRAP: divu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1b]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $4,$0,$0
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
# CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $0, $4, $5
# CHECK-NOTRAP: divu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1b]
divu $25, $11
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
# CHECK-TRAP: divu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1b]
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
divu $24,$12
# CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
# CHECK-TRAP: divu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1b]
# CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
divu $25,$0
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
# CHECK-TRAP: divu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1b]
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
divu $0,$9
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
# CHECK-TRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
divu $0,$0
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
# CHECK-TRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
divu $4,$5,$6
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
# CHECK-TRAP: divu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1b]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $4,$5,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
# CHECK-TRAP: divu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1b]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $4,$0,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
# CHECK-TRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $0, $4, $5
# CHECK-TRAP: divu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1b]