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llvm-project/llvm/test/MC/Mips/micromips-dspr2/invalid.s

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[mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions Differential Revision: http://reviews.llvm.org/D14010 llvm-svn: 253041
2015-11-13 21:14:25 +08:00
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 2>%t1
# RUN: FileCheck %s < %t1
[mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, CMPGU* and CMPU* instructions Differential Revision: http://reviews.llvm.org/D16182 llvm-svn: 269752
2016-05-17 17:32:58 +08:00
balign $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
balign $2, $3, 4 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
[mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions Differential Revision: http://reviews.llvm.org/D14010 llvm-svn: 253041
2015-11-13 21:14:25 +08:00
shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
shra_r.qb $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
shrl.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shrl.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
[mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and MULSAQ_S.W.PH instructions Differential Revision: http://reviews.llvm.org/D14117 llvm-svn: 269408
2016-05-13 19:32:53 +08:00
append $3, $4, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
append $3, $4, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
mulsa.w.ph $8, $3, $2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
mulsa.w.ph $31, $3, $2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
mulsaq_s.w.ph $8, $3, $2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
mulsaq_s.w.ph $31, $3, $2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
[mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, CMPGU* and CMPU* instructions Differential Revision: http://reviews.llvm.org/D16182 llvm-svn: 269752
2016-05-17 17:32:58 +08:00
# bposge32 is microMIPS DSP instruction but it is removed in Release 6
bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled