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llvm-project/llvm/test/MC/ARM/arm-thumb-trustzone.s

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Prefix failing commands with not to make clear they are expected to fail. llvm-svn: 185554
2013-07-04 00:41:29 +08:00
@ RUN: not llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
2013-04-10 20:08:35 +08:00
@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
Recognize that ARM1176JZ[F]-S support TrustZone Summary: ARMv6KZ cores were set up incorrectly in ARM.td; also, the SMI mnemonic (the old name for SMC, as defined in ARMv6KZ) wasn't supported. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14154 llvm-svn: 251627
2015-10-29 21:56:19 +08:00
@ RUN: not llvm-mc -triple=thumbv6kz -mcpu=arm1176jzf-s -show-encoding < %s | FileCheck %s -check-prefix=NOTZ
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
2013-04-10 20:08:35 +08:00
.syntax unified
.globl _func
@ Check that the assembler processes SMC instructions when TrustZone support is
@ active and that it rejects them when this feature is not enabled
_func:
@ CHECK: _func
@------------------------------------------------------------------------------
@ SMC
@------------------------------------------------------------------------------
smc #0xf
[ARM] Diagnose PC-writing instructions in IT blocks In Thumb2, instructions which write to the PC are UNPREDICTABLE if they are in an IT block but not the last instruction in the block. Previously, we only diagnosed this for LDM instructions, this patch extends the diagnostic to cover all of the relevant instructions. Differential Revision: https://reviews.llvm.org/D30398 llvm-svn: 296459
2017-02-28 18:04:36 +08:00
it eq
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
2013-04-10 20:08:35 +08:00
smceq #0
@ NOTZ-NOT: smc #15
@ NOTZ-NOT: smceq #0
@ TZ: smc #15 @ encoding: [0xff,0xf7,0x00,0x80]
[ARM] Diagnose PC-writing instructions in IT blocks In Thumb2, instructions which write to the PC are UNPREDICTABLE if they are in an IT block but not the last instruction in the block. Previously, we only diagnosed this for LDM instructions, this patch extends the diagnostic to cover all of the relevant instructions. Differential Revision: https://reviews.llvm.org/D30398 llvm-svn: 296459
2017-02-28 18:04:36 +08:00
@ TZ: it eq @ encoding: [0x08,0xbf]
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
2013-04-10 20:08:35 +08:00
@ TZ: smceq #0 @ encoding: [0xf0,0xf7,0x00,0x80]