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llvm-project/llvm/test/MC/AArch64/armv8.3a-rcpc.s

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[AArch64] Assembler support for v8.3 RCpc Added assembler and disassembler support for the new Release Consistent processor consistent instructions, introduced with ARM v8.3-A for AArch64. Differential Revision: https://reviews.llvm.org/D36522 llvm-svn: 310575
2017-08-10 17:52:55 +08:00
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
[ARM][AArch64] Cortex-A75 and Cortex-A55 support This patch introduces support for Cortex-A75 and Cortex-A55, Arm's latest big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including the cryptography and RAS extensions, plus the optional dot product extension. They also implement the RCpc AArch64 extension from ARMv8.3-A. Cortex-A75: https://developer.arm.com/products/processors/cortex-a/cortex-a75 Cortex-A55: https://developer.arm.com/products/processors/cortex-a/cortex-a55 Differential Revision: https://reviews.llvm.org/D36667 llvm-svn: 311316
2017-08-21 16:43:06 +08:00
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a75 < %s 2>&1 | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a55 < %s 2>&1 | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
[AArch64] Assembler support for v8.3 RCpc Added assembler and disassembler support for the new Release Consistent processor consistent instructions, introduced with ARM v8.3-A for AArch64. Differential Revision: https://reviews.llvm.org/D36522 llvm-svn: 310575
2017-08-10 17:52:55 +08:00
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
ldaprb w0, [x0, #0]
ldaprh w0, [x17, #0]
ldapr w0, [x1, #0]
ldapr x0, [x0, #0]
ldapr w18, [x0]
ldapr x15, [x0]
// CHECK: ldaprb w0, [x0] // encoding: [0x00,0xc0,0xbf,0x38]
// CHECK: ldaprh w0, [x17] // encoding: [0x20,0xc2,0xbf,0x78]
// CHECK: ldapr w0, [x1] // encoding: [0x20,0xc0,0xbf,0xb8]
// CHECK: ldapr x0, [x0] // encoding: [0x00,0xc0,0xbf,0xf8]
// CHECK: ldapr w18, [x0] // encoding: [0x12,0xc0,0xbf,0xb8]
// CHECK: ldapr x15, [x0] // encoding: [0x0f,0xc0,0xbf,0xf8]
[AArch64][SVE] Re-submit patch series for ZIP1/ZIP2 This patch resubmits the SVE ZIP1/ZIP2 patch series consisting of of r320992, r320986, r320973, and r320970 by reverting https://reviews.llvm.org/rL321024. The issue that caused r321024 has been addressed in https://reviews.llvm.org/rL321158, so this patch-series should be safe to resubmit. llvm-svn: 321163
2017-12-20 19:02:42 +08:00
// CHECK-REQ: error: instruction requires: rcpc
// CHECK-REQ: error: instruction requires: rcpc
// CHECK-REQ: error: instruction requires: rcpc
// CHECK-REQ: error: instruction requires: rcpc
[AArch64] Assembler support for v8.3 RCpc Added assembler and disassembler support for the new Release Consistent processor consistent instructions, introduced with ARM v8.3-A for AArch64. Differential Revision: https://reviews.llvm.org/D36522 llvm-svn: 310575
2017-08-10 17:52:55 +08:00
// CHECK-REQ: error: instruction requires: rcpc
// CHECK-REQ: error: instruction requires: rcpc