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llvm-project/llvm/test/CodeGen/MSP430/BranchSelector.ll

589 lines
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LLVM
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Fix PR27500: on MSP430 the branch destination offset is measured in words, not bytes. Summary: In addition, the branch instructions will have proper BB destinations, not offsets, like before. Reviewers: asl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23718 llvm-svn: 286252
2016-11-09 01:19:59 +08:00
; RUN: llc < %s -march=msp430 | FileCheck %s
target datalayout = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"
target triple = "msp430"
@reg = common global i16 0, align 2
define void @WriteBurstPATable(i16 %count) #0 {
entry:
br label %while.cond
while.cond:
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
%v0 = load volatile i16, i16* @reg, align 2
%lnot = icmp eq i16 %v0, 0
; This BB should be split and all branches should be expanded.
; CHECK-LABEL: .LBB0_1:
; CHECK: jne .LBB0_2
; CHECK: br #.LBB0_1
; CHECK: .LBB0_2:
; CHECK: br #.LBB0_4
; CHECK: .LBB0_3:
br i1 %lnot, label %while.cond, label %while.end
while.end:
%i.0.i.0.1822 = load volatile i16, i16* @reg, align 1
%cmp23 = icmp ult i16 %i.0.i.0.1822, %count
br i1 %cmp23, label %for.body, label %for.end
for.body:
br label %while.cond6
while.cond6:
%0 = load volatile i16, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 19, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
br label %for.inc
for.inc:
%1 = load volatile i16, i16* @reg, align 2
%cmp = icmp ult i16 %1, %count
; This branch should be expanded.
; CHECK-LABEL: .LBB0_4:
; CHECK: jhs .LBB0_5
; CHECK: br #.LBB0_3
; CHECK: .LBB0_5:
br i1 %cmp, label %for.body, label %for.end
for.end:
ret void
}
define void @WriteSinglePATable() #0 {
entry:
br label %begin
begin:
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
store volatile i16 13, i16* @reg, align 2
store volatile i16 17, i16* @reg, align 2
store volatile i16 11, i16* @reg, align 2
%v2 = load volatile i16, i16* @reg, align 2
%lnot = icmp eq i16 %v2, 0
; This branch should not be expanded
; CHECK-LABEL: .LBB1_1:
; CHECK: jeq .LBB1_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: %bb.2:
Fix PR27500: on MSP430 the branch destination offset is measured in words, not bytes. Summary: In addition, the branch instructions will have proper BB destinations, not offsets, like before. Reviewers: asl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23718 llvm-svn: 286252
2016-11-09 01:19:59 +08:00
; CHECK: ret
br i1 %lnot, label %begin, label %end
end:
ret void
}