forked from OSchip/llvm-project
31 lines
959 B
LLVM
31 lines
959 B
LLVM
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; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
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; generate vmems for W_equals_W (vassignp)
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; CHECK: vmem
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; CHECK: vmem
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; CHECK: vmem
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; CHECK: vmem
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target triple = "hexagon"
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@g0 = common global [15 x <32 x i32>] zeroinitializer, align 64
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@g1 = common global <32 x i32> zeroinitializer, align 64
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; Function Attrs: nounwind
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define i32 @f0() #0 {
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b0:
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%v0 = alloca i32, align 4
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%v1 = alloca i32, align 4
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store i32 0, i32* %v0
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store i32 0, i32* %v1, align 4
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%v2 = load <32 x i32>, <32 x i32>* getelementptr inbounds ([15 x <32 x i32>], [15 x <32 x i32>]* @g0, i32 0, i32 0), align 64
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%v3 = call <32 x i32> @llvm.hexagon.V6.vassignp(<32 x i32> %v2)
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store <32 x i32> %v3, <32 x i32>* @g1, align 64
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ret i32 0
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}
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vassignp(<32 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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