2016-10-31 23:45:09 +08:00
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# RUN: llc -march=hexagon -run-pass expand-condsets -expand-condsets-coa-limit=0 -o - %s -verify-machineinstrs | FileCheck %s
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# CHECK-LABEL: name: fred
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--- |
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define void @fred() { ret void }
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...
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---
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name: fred
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tracksRegLiveness: true
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registers:
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- { id: 0, class: predregs }
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- { id: 1, class: intregs }
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- { id: 2, class: intregs }
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- { id: 3, class: intregs }
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body: |
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bb.0:
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2018-02-01 06:04:26 +08:00
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liveins: $r0, $r1, $r2, $p0
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%0 = COPY $p0
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%0 = COPY $p0 ; Cheat: convince MIR parser that this is not SSA.
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%1 = COPY $r1
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2016-10-31 23:45:09 +08:00
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; Make sure we do not expand/predicate a mux with identical inputs.
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; CHECK-NOT: A2_paddit
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%2 = A2_addi %1, 1
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%3 = C2_mux %0, killed %2, %2
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2018-02-01 06:04:26 +08:00
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$r0 = COPY %3
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2016-10-31 23:45:09 +08:00
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...
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