forked from OSchip/llvm-project
38 lines
878 B
LLVM
38 lines
878 B
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: {{.balign 4|.p2align 2}}
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; CHECK: {{.balign 4|.p2align 2}}
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; CHECK: {{.balign 4|.p2align 2}}
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target triple = "hexagon"
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@g0 = global i32 4, align 4
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@g1 = global i32 4, align 4
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@g2 = global i32 4, align 4
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@g3 = global i32 4, align 4
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; Function Attrs: nounwind optsize
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define void @f0(i32 %a0) #0 {
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b0:
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store i32 1, i32* @g0, align 4
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ret void
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}
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; Function Attrs: nounwind optsize
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define void @f1(i32 %a0) #0 {
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b0:
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store i32 1, i32* @g0, align 4
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store i32 2, i32* @g1, align 4
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store i32 3, i32* @g2, align 4
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store i32 4, i32* @g3, align 4
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ret void
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}
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; Function Attrs: nounwind optsize readnone
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define i32 @f2(i32 %a0, i8** nocapture readnone %a1) #1 {
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b0:
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ret i32 %a0
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}
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attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" }
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attributes #1 = { nounwind optsize readnone "target-cpu"="hexagonv60" }
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