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llvm-project/llvm/test/CodeGen/Thumb2/thumb2-tst2.ll

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Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 07:44:19 +08:00
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
Explicitly request physreg coalesing for a bunch of Thumb2 unit tests. These tests all follow the same pattern: mov r2, r0 movs r0, #0 $CMP r2, r1 it eq moveq r0, #1 bx lr The first 'mov' can be eliminated by rematerializing 'movs r0, #0' below the test instruction: $CMP r0, r1 mov.w r0, #0 it eq moveq r0, #1 bx lr So far, only physreg coalescing can do that. The register allocators won't yet split live ranges just to eliminate copies. They can learn, but this particular problem is not likely to show up in real code. It only appears because r0 is used for both the function argument and return value. llvm-svn: 130858
2011-05-05 03:02:07 +08:00
Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 07:44:19 +08:00
; These tests would be improved by 'movs r0, #0' being rematerialized below the
; tst as 'mov.w r0, #0'.
Add Thumb-2 support for TEQ amd TST. llvm-svn: 74468
2009-06-30 06:49:42 +08:00
define i1 @f2(i32 %a, i32 %b) {
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck. llvm-svn: 78622
2009-08-11 07:56:04 +08:00
; CHECK: f2:
Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 07:44:19 +08:00
; CHECK: tst {{.*}}, r1
Add Thumb-2 support for TEQ amd TST. llvm-svn: 74468
2009-06-30 06:49:42 +08:00
%tmp = and i32 %a, %b
%tmp1 = icmp eq i32 %tmp, 0
ret i1 %tmp1
}
define i1 @f4(i32 %a, i32 %b) {
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck. llvm-svn: 78622
2009-08-11 07:56:04 +08:00
; CHECK: f4:
Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 07:44:19 +08:00
; CHECK: tst {{.*}}, r1
Add Thumb-2 support for TEQ amd TST. llvm-svn: 74468
2009-06-30 06:49:42 +08:00
%tmp = and i32 %a, %b
%tmp1 = icmp eq i32 0, %tmp
ret i1 %tmp1
}
Enhance tests to include shifted-register operand testing. llvm-svn: 74490
2009-06-30 09:02:20 +08:00
define i1 @f6(i32 %a, i32 %b) {
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck. llvm-svn: 78622
2009-08-11 07:56:04 +08:00
; CHECK: f6:
Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 07:44:19 +08:00
; CHECK: tst.w {{.*}}, r1, lsl #5
Enhance tests to include shifted-register operand testing. llvm-svn: 74490
2009-06-30 09:02:20 +08:00
%tmp = shl i32 %b, 5
%tmp1 = and i32 %a, %tmp
%tmp2 = icmp eq i32 %tmp1, 0
ret i1 %tmp2
}
define i1 @f7(i32 %a, i32 %b) {
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck. llvm-svn: 78622
2009-08-11 07:56:04 +08:00
; CHECK: f7:
Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 07:44:19 +08:00
; CHECK: tst.w {{.*}}, r1, lsr #6
Enhance tests to include shifted-register operand testing. llvm-svn: 74490
2009-06-30 09:02:20 +08:00
%tmp = lshr i32 %b, 6
%tmp1 = and i32 %a, %tmp
%tmp2 = icmp eq i32 %tmp1, 0
ret i1 %tmp2
}
define i1 @f8(i32 %a, i32 %b) {
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck. llvm-svn: 78622
2009-08-11 07:56:04 +08:00
; CHECK: f8:
Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 07:44:19 +08:00
; CHECK: tst.w {{.*}}, r1, asr #7
Enhance tests to include shifted-register operand testing. llvm-svn: 74490
2009-06-30 09:02:20 +08:00
%tmp = ashr i32 %b, 7
%tmp1 = and i32 %a, %tmp
%tmp2 = icmp eq i32 %tmp1, 0
ret i1 %tmp2
}
define i1 @f9(i32 %a, i32 %b) {
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck. llvm-svn: 78622
2009-08-11 07:56:04 +08:00
; CHECK: f9:
Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 07:44:19 +08:00
; CHECK: tst.w {{.*}}, {{.*}}, ror #8
Enhance tests to include shifted-register operand testing. llvm-svn: 74490
2009-06-30 09:02:20 +08:00
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
%tmp = or i32 %l8, %r8
%tmp1 = and i32 %a, %tmp
%tmp2 = icmp eq i32 %tmp1, 0
ret i1 %tmp2
}