2015-02-20 11:59:35 +08:00
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; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX1
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; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
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2014-09-21 16:49:27 +08:00
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target triple = "x86_64-unknown-unknown"
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define <8 x float> @shuffle_v8f32_00000000(<8 x float> %a, <8 x float> %b) {
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2014-10-01 06:04:45 +08:00
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; AVX1-LABEL: shuffle_v8f32_00000000:
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2014-09-25 19:03:55 +08:00
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; AVX1: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
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2014-09-25 19:03:55 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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2014-10-01 06:04:45 +08:00
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; AVX2-LABEL: shuffle_v8f32_00000000:
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2014-09-25 19:03:55 +08:00
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; AVX2: # BB#0:
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2014-10-01 08:41:21 +08:00
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; AVX2-NEXT: vbroadcastss %xmm0, %ymm0
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2014-09-25 19:03:55 +08:00
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; AVX2-NEXT: retq
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2014-09-21 16:49:27 +08:00
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x float> %shuffle
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}
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define <8 x float> @shuffle_v8f32_00000010(<8 x float> %a, <8 x float> %b) {
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2014-10-01 06:04:45 +08:00
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; AVX1-LABEL: shuffle_v8f32_00000010:
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2014-09-25 19:03:55 +08:00
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; AVX1: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,0,0,0]
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,0]
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2014-09-25 19:03:55 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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2014-10-01 06:04:45 +08:00
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; AVX2-LABEL: shuffle_v8f32_00000010:
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2014-09-25 19:03:55 +08:00
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; AVX2: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,0,0,1,0]
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2014-09-25 19:03:55 +08:00
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; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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2014-09-21 16:49:27 +08:00
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0>
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ret <8 x float> %shuffle
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}
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define <8 x float> @shuffle_v8f32_00000200(<8 x float> %a, <8 x float> %b) {
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2014-10-01 06:04:45 +08:00
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; AVX1-LABEL: shuffle_v8f32_00000200:
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2014-09-25 19:03:55 +08:00
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; AVX1: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,0,0,0]
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,0]
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2014-09-25 19:03:55 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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2014-10-01 06:04:45 +08:00
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; AVX2-LABEL: shuffle_v8f32_00000200:
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2014-09-25 19:03:55 +08:00
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; AVX2: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,0,2,0,0]
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2014-09-25 19:03:55 +08:00
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; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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2014-09-21 16:49:27 +08:00
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 0, i32 0>
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ret <8 x float> %shuffle
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}
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define <8 x float> @shuffle_v8f32_00003000(<8 x float> %a, <8 x float> %b) {
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2014-10-01 06:04:45 +08:00
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; AVX1-LABEL: shuffle_v8f32_00003000:
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2014-09-25 19:03:55 +08:00
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; AVX1: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,0,0,0]
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,0,0,0]
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2014-09-25 19:03:55 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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2014-10-01 06:04:45 +08:00
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; AVX2-LABEL: shuffle_v8f32_00003000:
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2014-09-25 19:03:55 +08:00
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; AVX2: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,3,0,0,0]
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2014-09-25 19:03:55 +08:00
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; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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2014-09-21 16:49:27 +08:00
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0>
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ret <8 x float> %shuffle
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}
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define <8 x float> @shuffle_v8f32_00040000(<8 x float> %a, <8 x float> %b) {
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2014-10-01 06:04:45 +08:00
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; AVX1-LABEL: shuffle_v8f32_00040000:
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2014-09-25 19:03:55 +08:00
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; AVX1: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
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; AVX1-NEXT: vpermilps {{.*#+}} ymm1 = ymm1[0,0,0,0,4,4,4,4]
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; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,3,4,4,4,7]
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; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3,4,5,6,7]
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2014-09-25 19:03:55 +08:00
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; AVX1-NEXT: retq
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;
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2014-10-01 06:04:45 +08:00
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; AVX2-LABEL: shuffle_v8f32_00040000:
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2014-09-25 19:03:55 +08:00
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; AVX2: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,4,0,0,0,0]
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2014-09-25 19:03:55 +08:00
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; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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2014-09-21 16:49:27 +08:00
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 0>
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ret <8 x float> %shuffle
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}
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define <8 x float> @shuffle_v8f32_00500000(<8 x float> %a, <8 x float> %b) {
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2014-10-01 06:04:45 +08:00
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; AVX1-LABEL: shuffle_v8f32_00500000:
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2014-09-25 19:03:55 +08:00
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; AVX1: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
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2015-02-15 20:42:15 +08:00
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; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
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; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,1,0,4,4,4,4]
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2014-09-25 19:03:55 +08:00
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; AVX1-NEXT: retq
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;
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2014-10-01 06:04:45 +08:00
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; AVX2-LABEL: shuffle_v8f32_00500000:
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2014-09-25 19:03:55 +08:00
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; AVX2: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,5,0,0,0,0,0]
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2014-09-25 19:03:55 +08:00
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; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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2014-09-21 16:49:27 +08:00
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x float> %shuffle
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}
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define <8 x float> @shuffle_v8f32_06000000(<8 x float> %a, <8 x float> %b) {
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2014-10-01 06:04:45 +08:00
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; AVX1-LABEL: shuffle_v8f32_06000000:
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2014-09-25 19:03:55 +08:00
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; AVX1: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
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2015-02-15 20:42:15 +08:00
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; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
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; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,0,0,4,4,4,4]
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2014-09-25 19:03:55 +08:00
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; AVX1-NEXT: retq
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;
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2014-10-01 06:04:45 +08:00
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; AVX2-LABEL: shuffle_v8f32_06000000:
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2014-09-25 19:03:55 +08:00
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; AVX2: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,6,0,0,0,0,0,0]
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2014-09-25 19:03:55 +08:00
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; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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2014-09-21 16:49:27 +08:00
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x float> %shuffle
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}
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define <8 x float> @shuffle_v8f32_70000000(<8 x float> %a, <8 x float> %b) {
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2014-10-01 06:04:45 +08:00
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; AVX1-LABEL: shuffle_v8f32_70000000:
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2014-09-25 19:03:55 +08:00
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; AVX1: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
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2015-02-15 20:42:15 +08:00
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; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
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; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,0,0,0,4,4,4,4]
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2014-09-25 19:03:55 +08:00
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; AVX1-NEXT: retq
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;
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2014-10-01 06:04:45 +08:00
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; AVX2-LABEL: shuffle_v8f32_70000000:
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2014-09-25 19:03:55 +08:00
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; AVX2: # BB#0:
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; AVX2-NEXT: movl $7, %eax
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2015-03-05 14:38:42 +08:00
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; AVX2-NEXT: vmovd %eax, %xmm1
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2014-09-25 19:03:55 +08:00
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; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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2014-09-21 16:49:27 +08:00
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x float> %shuffle
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}
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2015-01-27 05:28:32 +08:00
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define <8 x float> @shuffle_v8f32_01014545(<8 x float> %a, <8 x float> %b) {
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; ALL-LABEL: shuffle_v8f32_01014545:
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; ALL: # BB#0:
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; ALL-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
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; ALL-NEXT: retq
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>
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ret <8 x float> %shuffle
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2014-09-21 16:49:27 +08:00
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}
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define <8 x float> @shuffle_v8f32_00112233(<8 x float> %a, <8 x float> %b) {
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2014-10-01 06:04:45 +08:00
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; AVX1-LABEL: shuffle_v8f32_00112233:
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2014-09-25 19:03:55 +08:00
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; AVX1: # BB#0:
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2014-10-01 06:04:45 +08:00
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; AVX1-NEXT: vunpcklps {{.*#+}} xmm1 = xmm0[0,0,1,1]
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; AVX1-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2,2,3,3]
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2014-09-25 19:03:55 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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2014-10-01 06:04:45 +08:00
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; AVX2-LABEL: shuffle_v8f32_00112233:
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2014-09-25 19:03:55 +08:00
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; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
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; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,1,1,2,2,3,3]
|
2014-09-25 19:03:55 +08:00
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; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
|
2014-09-21 16:49:27 +08:00
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>
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ret <8 x float> %shuffle
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}
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define <8 x float> @shuffle_v8f32_00001111(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
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; AVX1-LABEL: shuffle_v8f32_00001111:
|
2014-09-25 19:03:55 +08:00
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; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
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; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,0,0,0]
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,1,1,1]
|
2014-09-25 19:03:55 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
|
2014-10-01 06:04:45 +08:00
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; AVX2-LABEL: shuffle_v8f32_00001111:
|
2014-09-25 19:03:55 +08:00
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; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
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; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,1,1,1,1]
|
2014-09-25 19:03:55 +08:00
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|
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
|
2014-09-21 16:49:27 +08:00
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|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1>
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ret <8 x float> %shuffle
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|
}
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|
2014-09-21 17:01:26 +08:00
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define <8 x float> @shuffle_v8f32_81a3c5e7(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
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|
; ALL-LABEL: shuffle_v8f32_81a3c5e7:
|
2014-09-21 17:01:26 +08:00
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|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
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|
; ALL-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
|
2014-09-21 17:01:26 +08:00
|
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|
; ALL-NEXT: retq
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|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>
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|
ret <8 x float> %shuffle
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|
}
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|
|
define <8 x float> @shuffle_v8f32_08080808(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8f32_08080808:
|
2015-01-27 05:28:32 +08:00
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,2,0]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
|
|
|
|
; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
|
|
|
; AVX1-NEXT: retq
|
2014-09-25 19:03:55 +08:00
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8f32_08080808:
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 08:41:21 +08:00
|
|
|
; AVX2-NEXT: vbroadcastss %xmm1, %ymm1
|
2014-10-03 05:37:14 +08:00
|
|
|
; AVX2-NEXT: vbroadcastsd %xmm0, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-21 17:01:26 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 0, i32 8, i32 0, i32 8>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_08084c4c(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_08084c4c:
|
2014-09-21 17:01:26 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[0,0],ymm0[4,4],ymm1[4,4]
|
|
|
|
; ALL-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7]
|
2014-09-21 17:01:26 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 4, i32 12, i32 4, i32 12>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_8823cc67(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_8823cc67:
|
2014-09-21 17:01:26 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,0],ymm0[2,3],ymm1[4,4],ymm0[6,7]
|
2014-09-21 17:01:26 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 8, i32 8, i32 2, i32 3, i32 12, i32 12, i32 6, i32 7>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_9832dc76(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_9832dc76:
|
2014-09-21 17:01:26 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vshufps {{.*#+}} ymm0 = ymm1[1,0],ymm0[3,2],ymm1[5,4],ymm0[7,6]
|
2014-09-21 17:01:26 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 9, i32 8, i32 3, i32 2, i32 13, i32 12, i32 7, i32 6>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_9810dc54(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_9810dc54:
|
2014-09-21 17:01:26 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vshufps {{.*#+}} ymm0 = ymm1[1,0],ymm0[1,0],ymm1[5,4],ymm0[5,4]
|
2014-09-21 17:01:26 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 9, i32 8, i32 1, i32 0, i32 13, i32 12, i32 5, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2014-09-21 20:13:11 +08:00
|
|
|
define <8 x float> @shuffle_v8f32_08194c5d(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_08194c5d:
|
2014-09-21 20:13:11 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
|
2014-09-21 20:13:11 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_2a3b6e7f(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_2a3b6e7f:
|
2014-09-21 20:13:11 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
|
2014-09-21 20:13:11 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2014-09-21 16:49:27 +08:00
|
|
|
define <8 x float> @shuffle_v8f32_08192a3b(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8f32_08192a3b:
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-11-13 12:06:10 +08:00
|
|
|
; AVX1-NEXT: vunpckhps {{.*#+}} xmm2 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
|
|
|
; AVX1-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8f32_08192a3b:
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <u,0,u,1,u,2,u,3>
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: vpermps %ymm1, %ymm2, %ymm1
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <0,u,1,u,2,u,3,u>
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: vpermps %ymm0, %ymm2, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-21 16:49:27 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_08991abb(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8f32_08991abb:
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX1: # BB#0:
|
2015-02-15 16:26:30 +08:00
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,0],xmm1[0,0]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,1]
|
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8f32_08991abb:
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <0,u,u,u,1,u,u,u>
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: vpermps %ymm0, %ymm2, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <u,0,1,1,u,2,3,3>
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: vpermps %ymm1, %ymm2, %ymm1
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-21 16:49:27 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 8, i32 9, i32 9, i32 1, i32 10, i32 11, i32 11>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_091b2d3f(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8f32_091b2d3f:
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[0,1,1,3]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,1,3,3]
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8f32_091b2d3f:
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <0,u,1,u,2,u,3,u>
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: vpermps %ymm0, %ymm2, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-21 16:49:27 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 9, i32 1, i32 11, i32 2, i32 13, i32 3, i32 15>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-01-27 05:28:32 +08:00
|
|
|
define <8 x float> @shuffle_v8f32_09ab1def(<8 x float> %a, <8 x float> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8f32_09ab1def:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
|
|
|
|
; AVX1-NEXT: retq
|
2014-09-25 19:03:55 +08:00
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8f32_09ab1def:
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <0,u,u,u,1,u,u,u>
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: vpermps %ymm0, %ymm2, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-21 16:49:27 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 1, i32 13, i32 14, i32 15>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_00014445(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_00014445:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,1,4,4,4,5]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 4, i32 4, i32 4, i32 5>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_00204464(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_00204464:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,0,4,4,6,4]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 4, i32 6, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_03004744(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_03004744:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,3,0,0,4,7,4,4]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 7, i32 4, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_10005444(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_10005444:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,0,0,5,4,4,4]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 5, i32 4, i32 4, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_22006644(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_22006644:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,2,0,0,6,6,4,4]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 6, i32 4, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_33307774(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_33307774:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,3,0,7,7,7,4]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 7, i32 7, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_32107654(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_32107654:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_00234467(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_00234467:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,3,4,4,6,7]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 4, i32 4, i32 6, i32 7>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-01-27 05:28:32 +08:00
|
|
|
define <8 x float> @shuffle_v8f32_00224466(<8 x float> %a, <8 x float> %b) {
|
|
|
|
; ALL-LABEL: shuffle_v8f32_00224466:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
|
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
|
|
|
|
ret <8 x float> %shuffle
|
2014-09-21 16:49:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_10325476(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_10325476:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,5,4,7,6]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-01-27 05:28:32 +08:00
|
|
|
define <8 x float> @shuffle_v8f32_11335577(<8 x float> %a, <8 x float> %b) {
|
|
|
|
; ALL-LABEL: shuffle_v8f32_11335577:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
|
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
|
|
|
|
ret <8 x float> %shuffle
|
2014-09-21 16:49:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_10235467(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_10235467:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,2,3,5,4,6,7]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 5, i32 4, i32 6, i32 7>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_10225466(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_10225466:
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,2,2,5,4,6,6]
|
2014-09-21 16:49:27 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 0, i32 2, i32 2, i32 5, i32 4, i32 6, i32 6>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
2014-09-22 07:32:42 +08:00
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_00015444(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_00015444:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,1,5,4,4,4]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 5, i32 4, i32 4, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_00204644(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_00204644:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,0,4,6,4,4]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 6, i32 4, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_03004474(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_03004474:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,3,0,0,4,4,7,4]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 4, i32 7, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_10004444(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_10004444:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,0,0,4,4,4,4]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_22006446(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_22006446:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,2,0,0,6,4,4,6]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 4, i32 4, i32 6>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_33307474(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_33307474:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,3,0,7,4,7,4]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 4, i32 7, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_32104567(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_32104567:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,4,5,6,7]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_00236744(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_00236744:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,3,6,7,4,4]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 6, i32 7, i32 4, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_00226644(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_00226644:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,2,6,6,4,4]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 6, i32 6, i32 4, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_10324567(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_10324567:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,4,5,6,7]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_11334567(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_11334567:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,1,3,3,4,5,6,7]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_01235467(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_01235467:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,1,2,3,5,4,6,7]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 7>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_01235466(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_01235466:
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,1,2,3,5,4,6,6]
|
2014-09-22 07:32:42 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 6>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
2014-09-22 07:46:13 +08:00
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_002u6u44(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_002u6u44:
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,u,6,u,4,4]
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 4, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_00uu66uu(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_00uu66uu:
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,u,u,6,6,u,u]
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 undef, i32 undef, i32 6, i32 6, i32 undef, i32 undef>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_103245uu(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_103245uu:
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,4,5,u,u]
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 undef, i32 undef>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_1133uu67(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_1133uu67:
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,1,3,3,u,u,6,7]
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 undef, i32 6, i32 7>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_0uu354uu(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_0uu354uu:
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,u,u,3,5,4,u,u]
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 5, i32 4, i32 undef, i32 undef>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_uuu3uu66(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_uuu3uu66:
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[u,u,u,3,u,u,6,6]
|
2014-09-22 07:46:13 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 6>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
2014-09-23 04:25:08 +08:00
|
|
|
|
2014-09-27 01:11:02 +08:00
|
|
|
define <8 x float> @shuffle_v8f32_c348cda0(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8f32_c348cda0:
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,0,1]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,3],ymm2[0,0],ymm0[4,7],ymm2[4,4]
|
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm1[2,3,0,1]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm1 = ymm1[0,1,2,0,4,5,6,4]
|
2014-10-03 05:37:14 +08:00
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} ymm1 = ymm2[0],ymm1[1,2],ymm2[3]
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2],ymm1[3,4,5,6],ymm0[7]
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8f32_c348cda0:
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <u,3,4,u,u,u,u,0>
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX2-NEXT: vpermps %ymm0, %ymm2, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <4,u,u,0,4,5,2,u>
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX2-NEXT: vpermps %ymm1, %ymm2, %ymm1
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2],ymm1[3,4,5,6],ymm0[7]
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 12, i32 3, i32 4, i32 8, i32 12, i32 13, i32 10, i32 0>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2014-09-27 01:24:26 +08:00
|
|
|
define <8 x float> @shuffle_v8f32_f511235a(<8 x float> %a, <8 x float> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8f32_f511235a:
|
2014-09-27 01:24:26 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,0,1]
|
2014-10-03 05:37:14 +08:00
|
|
|
; AVX1-NEXT: vpermilpd {{.*#+}} ymm2 = ymm2[0,0,3,2]
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,1,1,1,4,5,5,5]
|
2014-10-03 05:37:14 +08:00
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm2[0],ymm0[1],ymm2[2],ymm0[3]
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm1[2,3,0,1]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm1 = ymm1[3,1,2,2,7,5,6,6]
|
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6],ymm1[7]
|
2014-09-27 01:24:26 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8f32_f511235a:
|
2014-09-27 01:24:26 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <7,u,u,u,u,u,u,2>
|
2014-09-27 01:24:26 +08:00
|
|
|
; AVX2-NEXT: vpermps %ymm1, %ymm2, %ymm1
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <u,5,1,1,2,3,5,u>
|
2014-09-27 01:24:26 +08:00
|
|
|
; AVX2-NEXT: vpermps %ymm0, %ymm2, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6],ymm1[7]
|
2014-09-27 01:24:26 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 15, i32 5, i32 1, i32 1, i32 2, i32 3, i32 5, i32 10>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2014-11-14 06:49:44 +08:00
|
|
|
define <8 x float> @shuffle_v8f32_32103210(<8 x float> %a, <8 x float> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8f32_32103210:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8f32_32103210:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [3,2,1,0,3,2,1,0]
|
|
|
|
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_76547654(<8 x float> %a, <8 x float> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8f32_76547654:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8f32_76547654:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
|
|
|
|
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_76543210(<8 x float> %a, <8 x float> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8f32_76543210:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8f32_76543210:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [7,6,5,4,3,2,1,0]
|
|
|
|
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_3210ba98(<8 x float> %a, <8 x float> %b) {
|
2014-11-21 21:56:05 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_3210ba98:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
|
|
|
; ALL-NEXT: retq
|
2014-11-14 06:49:44 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 11, i32 10, i32 9, i32 8>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_3210fedc(<8 x float> %a, <8 x float> %b) {
|
2014-11-21 22:33:24 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_3210fedc:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
|
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
|
|
|
; ALL-NEXT: retq
|
2014-11-14 06:49:44 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_7654fedc(<8 x float> %a, <8 x float> %b) {
|
2014-11-21 21:56:05 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_7654fedc:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
|
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
|
|
|
; ALL-NEXT: retq
|
2014-11-14 06:49:44 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_fedc7654(<8 x float> %a, <8 x float> %b) {
|
2014-11-21 21:56:05 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_fedc7654:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
|
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
|
|
|
; ALL-NEXT: retq
|
2014-11-14 06:49:44 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 7, i32 6, i32 5, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-02-16 02:21:39 +08:00
|
|
|
define <8 x float> @PR21138(<8 x float> %truc, <8 x float> %tchose) {
|
|
|
|
; AVX1-LABEL: PR21138:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,3]
|
2015-02-16 14:29:02 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
|
2015-02-16 02:21:39 +08:00
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm2[1,3]
|
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: PR21138:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <u,u,u,u,1,3,5,7>
|
|
|
|
; AVX2-NEXT: vpermps %ymm1, %ymm2, %ymm1
|
|
|
|
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <1,3,5,7,u,u,u,u>
|
|
|
|
; AVX2-NEXT: vpermps %ymm0, %ymm2, %ymm0
|
|
|
|
; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %truc, <8 x float> %tchose, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2014-11-14 06:49:44 +08:00
|
|
|
define <8 x float> @shuffle_v8f32_ba987654(<8 x float> %a, <8 x float> %b) {
|
2014-11-21 22:33:24 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_ba987654:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
|
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
|
|
|
; ALL-NEXT: retq
|
2014-11-14 06:49:44 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_ba983210(<8 x float> %a, <8 x float> %b) {
|
2014-11-21 22:33:24 +08:00
|
|
|
; ALL-LABEL: shuffle_v8f32_ba983210:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
|
|
|
|
; ALL-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
|
|
|
; ALL-NEXT: retq
|
2014-11-14 06:49:44 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-02-18 06:24:32 +08:00
|
|
|
define <8 x float> @shuffle_v8f32_80u1c4u5(<8 x float> %a, <8 x float> %b) {
|
|
|
|
; ALL-LABEL: shuffle_v8f32_80u1c4u5:
|
2015-02-15 23:07:45 +08:00
|
|
|
; ALL: # BB#0:
|
2015-02-18 06:24:32 +08:00
|
|
|
; ALL-NEXT: vunpcklps {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[4],ymm0[4],ymm1[5],ymm0[5]
|
2015-02-15 23:07:45 +08:00
|
|
|
; ALL-NEXT: retq
|
2015-02-18 06:24:32 +08:00
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 8, i32 0, i32 undef, i32 1, i32 12, i32 4, i32 undef, i32 5>
|
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @shuffle_v8f32_a2u3e6f7(<8 x float> %a, <8 x float> %b) {
|
|
|
|
; ALL-LABEL: shuffle_v8f32_a2u3e6f7:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vunpckhps {{.*#+}} ymm0 = ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[6],ymm0[6],ymm1[7],ymm0[7]
|
|
|
|
; ALL-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 10, i32 2, i32 undef, i32 3, i32 14, i32 6, i32 15, i32 7>
|
2015-02-15 23:07:45 +08:00
|
|
|
ret <8 x float> %shuffle
|
|
|
|
}
|
|
|
|
|
2014-09-23 04:25:08 +08:00
|
|
|
define <8 x i32> @shuffle_v8i32_00000000(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00000000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00000000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 08:41:21 +08:00
|
|
|
; AVX2-NEXT: vbroadcastss %xmm0, %ymm0
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00000010(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00000010:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,0,0,0]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,0]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00000010:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,0,0,0,0,1,0]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00000200(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00000200:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,0,0,0]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,0]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00000200:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,0,0,0,2,0,0]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 0, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00003000(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00003000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,0,0,0]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,0,0,0]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00003000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,0,0,3,0,0,0]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00040000(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00040000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm1 = ymm1[0,0,0,0,4,4,4,4]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,3,4,4,4,7]
|
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3,4,5,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00040000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,0,4,0,0,0,0]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00500000(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00500000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
|
2015-02-15 20:42:15 +08:00
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,1,0,4,4,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00500000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,5,0,0,0,0,0]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_06000000(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_06000000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
|
2015-02-15 20:42:15 +08:00
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,0,0,4,4,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_06000000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,6,0,0,0,0,0,0]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_70000000(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_70000000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
|
2015-02-15 20:42:15 +08:00
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,0,0,0,4,4,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_70000000:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: movl $7, %eax
|
2015-03-05 14:38:42 +08:00
|
|
|
; AVX2-NEXT: vmovd %eax, %xmm1
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-01-27 05:28:32 +08:00
|
|
|
define <8 x i32> @shuffle_v8i32_01014545(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_01014545:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_01014545:
|
2014-09-24 06:39:02 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5]
|
2014-09-24 06:39:02 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00112233(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00112233:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2015-02-15 18:12:02 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,0,1,1]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00112233:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,1,1,2,2,3,3]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00001111(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00001111:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,0,0,0]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,1,1,1]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00001111:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,0,0,1,1,1,1]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_81a3c5e7(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_81a3c5e7:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_81a3c5e7:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_08080808(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_08080808:
|
2015-01-27 05:28:32 +08:00
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,2,0]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
|
|
|
|
; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
|
|
|
; AVX1-NEXT: retq
|
2014-09-24 09:24:44 +08:00
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_08080808:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 08:41:21 +08:00
|
|
|
; AVX2-NEXT: vpbroadcastd %xmm1, %ymm1
|
|
|
|
; AVX2-NEXT: vpbroadcastq %xmm0, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 0, i32 8, i32 0, i32 8>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_08084c4c(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_08084c4c:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[0,0],ymm0[4,4],ymm1[4,4]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_08084c4c:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,2,0,4,4,6,4]
|
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5]
|
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 4, i32 12, i32 4, i32 12>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_8823cc67(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_8823cc67:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,0],ymm0[2,3],ymm1[4,4],ymm0[6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_8823cc67:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,0,2,3,4,4,6,7]
|
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 8, i32 8, i32 2, i32 3, i32 12, i32 12, i32 6, i32 7>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_9832dc76(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_9832dc76:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[1,0],ymm0[3,2],ymm1[5,4],ymm0[7,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_9832dc76:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
|
2015-02-15 20:42:15 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,0,3,2,5,4,7,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 9, i32 8, i32 3, i32 2, i32 13, i32 12, i32 7, i32 6>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_9810dc54(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_9810dc54:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[1,0],ymm0[1,0],ymm1[5,4],ymm0[5,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_9810dc54:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,1,1,0,4,5,5,4]
|
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[1,0,2,3,5,4,6,7]
|
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 9, i32 8, i32 1, i32 0, i32 13, i32 12, i32 5, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_08194c5d(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_08194c5d:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_08194c5d:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_2a3b6e7f(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_2a3b6e7f:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_2a3b6e7f:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpunpckhdq {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_08192a3b(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_08192a3b:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-11-13 12:06:10 +08:00
|
|
|
; AVX1-NEXT: vunpckhps {{.*#+}} xmm2 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
|
|
|
; AVX1-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_08192a3b:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = <u,0,u,1,u,2,u,3>
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm1, %ymm2, %ymm1
|
2015-02-04 03:34:09 +08:00
|
|
|
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_08991abb(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_08991abb:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2015-02-15 16:26:30 +08:00
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,0],xmm1[0,0]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,1]
|
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_08991abb:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = <0,u,u,u,1,u,u,u>
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm2, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = <u,0,1,1,u,2,3,3>
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm1, %ymm2, %ymm1
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 9, i32 9, i32 1, i32 10, i32 11, i32 11>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_091b2d3f(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_091b2d3f:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[0,1,1,3]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,1,3,3]
|
2014-09-25 19:03:55 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_091b2d3f:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2015-02-04 03:34:09 +08:00
|
|
|
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 9, i32 1, i32 11, i32 2, i32 13, i32 3, i32 15>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-01-27 05:28:32 +08:00
|
|
|
define <8 x i32> @shuffle_v8i32_09ab1def(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_09ab1def:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
|
|
|
|
; AVX1-NEXT: retq
|
2014-09-24 09:24:44 +08:00
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_09ab1def:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = <0,u,u,u,1,u,u,u>
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm2, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 1, i32 13, i32 14, i32 15>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00014445(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00014445:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,1,4,4,4,5]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00014445:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,0,1,4,4,4,5]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 4, i32 4, i32 4, i32 5>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00204464(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00204464:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,0,4,4,6,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00204464:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,2,0,4,4,6,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 4, i32 6, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_03004744(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_03004744:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,3,0,0,4,7,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_03004744:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,3,0,0,4,7,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 7, i32 4, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_10005444(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_10005444:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,0,0,5,4,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_10005444:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,0,0,0,5,4,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 5, i32 4, i32 4, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_22006644(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_22006644:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,2,0,0,6,6,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_22006644:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,2,0,0,6,6,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 6, i32 4, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_33307774(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_33307774:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,3,0,7,7,7,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_33307774:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,3,3,0,7,7,7,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 7, i32 7, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_32107654(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_32107654:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_32107654:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00234467(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00234467:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,3,4,4,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00234467:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,2,3,4,4,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 4, i32 4, i32 6, i32 7>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-01-27 05:28:32 +08:00
|
|
|
define <8 x i32> @shuffle_v8i32_00224466(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_00224466:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_00224466:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_10325476(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_10325476:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,5,4,7,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_10325476:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,0,3,2,5,4,7,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-01-27 05:28:32 +08:00
|
|
|
define <8 x i32> @shuffle_v8i32_11335577(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_11335577:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_11335577:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_10235467(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_10235467:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,2,3,5,4,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_10235467:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,0,2,3,5,4,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 5, i32 4, i32 6, i32 7>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_10225466(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_10225466:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,2,2,5,4,6,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_10225466:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,0,2,2,5,4,6,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 0, i32 2, i32 2, i32 5, i32 4, i32 6, i32 6>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00015444(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00015444:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,1,5,4,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00015444:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,0,1,5,4,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 5, i32 4, i32 4, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00204644(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00204644:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,0,4,6,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00204644:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,2,0,4,6,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 6, i32 4, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_03004474(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_03004474:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,3,0,0,4,4,7,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_03004474:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,3,0,0,4,4,7,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 4, i32 7, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_10004444(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_10004444:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,0,0,4,4,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_10004444:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1,0,0,0,4,4,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_22006446(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_22006446:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,2,0,0,6,4,4,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_22006446:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [2,2,0,0,6,4,4,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 4, i32 4, i32 6>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_33307474(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_33307474:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,3,0,7,4,7,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_33307474:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [3,3,3,0,7,4,7,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 4, i32 7, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_32104567(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_32104567:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,4,5,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_32104567:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [3,2,1,0,4,5,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00236744(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00236744:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,3,6,7,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00236744:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,2,3,6,7,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 6, i32 7, i32 4, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00226644(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00226644:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,2,6,6,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00226644:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,2,2,6,6,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 6, i32 6, i32 4, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_10324567(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_10324567:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,4,5,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_10324567:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1,0,3,2,4,5,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_11334567(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_11334567:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,1,3,3,4,5,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_11334567:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1,1,3,3,4,5,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_01235467(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_01235467:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,1,2,3,5,4,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_01235467:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,5,4,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 7>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_01235466(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_01235466:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,1,2,3,5,4,6,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_01235466:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,5,4,6,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 6>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_002u6u44(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_002u6u44:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,u,6,u,4,4]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_002u6u44:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = <0,0,2,u,6,u,4,4>
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 4, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_00uu66uu(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_00uu66uu:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,u,u,6,6,u,u]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_00uu66uu:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = <0,0,u,u,6,6,u,u>
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 undef, i32 undef, i32 6, i32 6, i32 undef, i32 undef>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_103245uu(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_103245uu:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,4,5,u,u]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_103245uu:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = <1,0,3,2,4,5,u,u>
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 undef, i32 undef>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_1133uu67(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_1133uu67:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,1,3,3,u,u,6,7]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_1133uu67:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = <1,1,3,3,u,u,6,7>
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 undef, i32 6, i32 7>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_0uu354uu(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_0uu354uu:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,u,u,3,5,4,u,u]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_0uu354uu:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = <0,u,u,3,5,4,u,u>
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 5, i32 4, i32 undef, i32 undef>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_uuu3uu66(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_uuu3uu66:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[u,u,u,3,u,u,6,6]
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_uuu3uu66:
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = <u,u,u,3,u,u,6,6>
|
2014-09-24 09:24:44 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
2014-09-23 04:25:08 +08:00
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 6>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
2014-09-27 01:11:02 +08:00
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_6caa87e5(<8 x i32> %a, <8 x i32> %b) {
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-LABEL: shuffle_v8i32_6caa87e5:
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX1: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm1[2,3,0,1]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm1 = ymm2[0,0],ymm1[2,2],ymm2[4,4],ymm1[6,6]
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
2014-10-03 05:37:14 +08:00
|
|
|
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4],ymm0[5],ymm1[6],ymm0[7]
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-LABEL: shuffle_v8i32_6caa87e5:
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX2: # BB#0:
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = <u,4,2,2,0,u,6,u>
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX2-NEXT: vpermd %ymm1, %ymm2, %ymm1
|
2014-10-01 06:04:45 +08:00
|
|
|
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,1,3,2]
|
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4],ymm0[5],ymm1[6],ymm0[7]
|
2014-09-27 01:11:02 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 6, i32 12, i32 10, i32 10, i32 8, i32 7, i32 14, i32 5>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
2014-10-14 00:16:16 +08:00
|
|
|
|
2014-11-14 06:49:44 +08:00
|
|
|
define <8 x i32> @shuffle_v8i32_32103210(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_32103210:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_32103210:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [3,2,1,0,3,2,1,0]
|
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_76547654(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_76547654:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_76547654:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
|
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_76543210(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_76543210:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_76543210:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,3,2,1,0]
|
|
|
|
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_3210ba98(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_3210ba98:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
2014-11-21 21:56:05 +08:00
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_3210ba98:
|
|
|
|
; AVX2: # BB#0:
|
2014-11-21 21:56:05 +08:00
|
|
|
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 11, i32 10, i32 9, i32 8>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_3210fedc(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_3210fedc:
|
|
|
|
; AVX1: # BB#0:
|
2014-11-21 22:33:24 +08:00
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_3210fedc:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
|
2014-11-21 22:33:24 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_7654fedc(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_7654fedc:
|
|
|
|
; AVX1: # BB#0:
|
2014-11-21 21:56:05 +08:00
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_7654fedc:
|
|
|
|
; AVX2: # BB#0:
|
2014-11-21 21:56:05 +08:00
|
|
|
; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
|
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_fedc7654(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_fedc7654:
|
|
|
|
; AVX1: # BB#0:
|
2014-11-21 21:56:05 +08:00
|
|
|
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_fedc7654:
|
|
|
|
; AVX2: # BB#0:
|
2014-11-21 21:56:05 +08:00
|
|
|
; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 7, i32 6, i32 5, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_ba987654(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_ba987654:
|
|
|
|
; AVX1: # BB#0:
|
2014-11-21 22:33:24 +08:00
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_ba987654:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
|
2014-11-21 22:33:24 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_ba983210(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_ba983210:
|
|
|
|
; AVX1: # BB#0:
|
2014-11-21 22:33:24 +08:00
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_ba983210:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
|
2014-11-21 22:33:24 +08:00
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
|
2014-11-14 06:49:44 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-02-15 21:19:52 +08:00
|
|
|
define <8 x i32> @shuffle_v8i32_zuu8zuuc(<8 x i32> %a) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_zuu8zuuc:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
2015-02-16 14:29:02 +08:00
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,0],ymm1[4,5],ymm0[6,4]
|
2015-02-15 21:19:52 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_zuu8zuuc:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19]
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> zeroinitializer, <8 x i32> %a, <8 x i32> <i32 0, i32 undef, i32 undef, i32 8, i32 0, i32 undef, i32 undef, i32 12>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_9ubzdefz(<8 x i32> %a) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_9ubzdefz:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
2015-02-16 14:29:02 +08:00
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm1 = ymm1[3,0],ymm0[3,0],ymm1[7,4],ymm0[7,4]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,2],ymm1[2,0],ymm0[5,6],ymm1[6,4]
|
2015-02-15 21:19:52 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_9ubzdefz:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,ymm0[20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero,zero
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> zeroinitializer, <8 x i32> %a, <8 x i32> <i32 9, i32 undef, i32 11, i32 0, i32 13, i32 14, i32 15, i32 0>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-02-15 23:07:45 +08:00
|
|
|
define <8 x i32> @shuffle_v8i32_80u1b4uu(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_80u1b4uu:
|
|
|
|
; AVX1: # BB#0:
|
2015-02-18 06:24:32 +08:00
|
|
|
; AVX1-NEXT: vunpcklps {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[4],ymm0[4],ymm1[5],ymm0[5]
|
2015-02-15 23:07:45 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_80u1b4uu:
|
|
|
|
; AVX2: # BB#0:
|
2015-02-18 06:24:32 +08:00
|
|
|
; AVX2-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[4],ymm0[4],ymm1[5],ymm0[5]
|
2015-02-15 23:07:45 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 8, i32 0, i32 undef, i32 1, i32 12, i32 4, i32 undef, i32 undef>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
2014-10-14 00:16:16 +08:00
|
|
|
define <8 x float> @splat_mem_v8f32_2(float* %p) {
|
|
|
|
; ALL-LABEL: splat_mem_v8f32_2:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vbroadcastss (%rdi), %ymm0
|
|
|
|
; ALL-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load float, float* %p
|
2014-10-14 00:16:16 +08:00
|
|
|
%2 = insertelement <4 x float> undef, float %1, i32 0
|
|
|
|
%3 = shufflevector <4 x float> %2, <4 x float> undef, <8 x i32> zeroinitializer
|
|
|
|
ret <8 x float> %3
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @splat_v8f32(<4 x float> %r) {
|
|
|
|
; AVX1-LABEL: splat_v8f32:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: splat_v8f32:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vbroadcastss %xmm0, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%1 = shufflevector <4 x float> %r, <4 x float> undef, <8 x i32> zeroinitializer
|
|
|
|
ret <8 x float> %1
|
|
|
|
}
|
Improve DAG combine pass on certain IR vector patterns
Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector
produced suboptimal code in AVX2 mode with certain IR combinations.
In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32
(undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical,
but then mysteriously generated rather bad code; the movq/movhpd combination
didn't match.
The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs
would get promoted to 4f32 by the type legalizer, eventually resulting
in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing
these were both half the output size, concatted them and then produced
a shuffle. However, the resulting concat + shuffle was more complex than
it should be; in the case where the upper half of the output is undef, we
probably want to generate shuffle + concat instead.
This enhancement causes the vector_shuffle combine step to recognize this
suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR
in case the same suboptimal pattern occurs for other reasons.
This results in the optimizer correctly producing the optimal movq + movhpd
sequence for all three variations on this IR, even with AVX2.
I've included a test case.
Radar link: rdar://problem/19287012
Fix for PR 21943.
From: Fiona Glaser <fglaser@apple.com>
llvm-svn: 226360
2015-01-17 09:35:56 +08:00
|
|
|
|
2015-02-04 05:58:29 +08:00
|
|
|
;
|
|
|
|
; Shuffle to logical bit shifts
|
|
|
|
;
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_z0U2zUz6(<8 x i32> %a) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_z0U2zUz6:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
2015-02-15 20:18:12 +08:00
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
|
2015-02-04 05:58:29 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_z0U2zUz6:
|
|
|
|
; AVX2: # BB#0:
|
2015-02-04 18:46:53 +08:00
|
|
|
; AVX2-NEXT: vpsllq $32, %ymm0, %ymm0
|
2015-02-04 05:58:29 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <8 x i32> <i32 8, i32 0, i32 undef, i32 2, i32 8, i32 undef, i32 8, i32 6>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_1U3z5zUU(<8 x i32> %a) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_1U3z5zUU:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
2015-02-15 20:18:12 +08:00
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7]
|
2015-02-04 05:58:29 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_1U3z5zUU:
|
|
|
|
; AVX2: # BB#0:
|
2015-02-04 18:46:53 +08:00
|
|
|
; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm0
|
2015-02-04 05:58:29 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 undef, i32 3, i32 8, i32 5, i32 8, i32 undef, i32 undef>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-02-16 14:29:06 +08:00
|
|
|
define <8 x i32> @shuffle_v8i32_B012F456(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_B012F456:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm1 = ymm1[3,0],ymm0[0,0],ymm1[7,4],ymm0[4,4]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,2],ymm0[1,2],ymm1[4,6],ymm0[5,6]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_B012F456:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm1[12,13,14,15],ymm0[0,1,2,3,4,5,6,7,8,9,10,11],ymm1[28,29,30,31],ymm0[16,17,18,19,20,21,22,23,24,25,26,27]
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 11, i32 0, i32 1, i32 2, i32 15, i32 4, i32 5, i32 6>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_1238567C(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_1238567C:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm1 = ymm1[0,0],ymm0[3,0],ymm1[4,4],ymm0[7,4]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,2],ymm1[2,0],ymm0[5,6],ymm1[6,4]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_1238567C:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0,1,2,3],ymm0[20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16,17,18,19]
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_9AB0DEF4(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_9AB0DEF4:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[3,0],ymm0[4,4],ymm1[7,4]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[1,2],ymm0[2,0],ymm1[5,6],ymm0[6,4]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_9AB0DEF4:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm1[4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0,1,2,3],ymm1[20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16,17,18,19]
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 9, i32 10, i32 11, i32 0, i32 13, i32 14, i32 15, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_389A7CDE(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_389A7CDE:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[3,0],ymm1[0,0],ymm0[7,4],ymm1[4,4]
|
|
|
|
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[1,2],ymm0[4,6],ymm1[5,6]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_389A7CDE:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[12,13,14,15],ymm1[0,1,2,3,4,5,6,7,8,9,10,11],ymm0[28,29,30,31],ymm1[16,17,18,19,20,21,22,23,24,25,26,27]
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 8, i32 9, i32 10, i32 7, i32 12, i32 13, i32 14>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_30127456(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_30127456:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,0,1,2,7,4,5,6]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_30127456:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,0,1,2,7,4,5,6]
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @shuffle_v8i32_12305674(<8 x i32> %a, <8 x i32> %b) {
|
|
|
|
; AVX1-LABEL: shuffle_v8i32_12305674:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,2,3,0,5,6,7,4]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: shuffle_v8i32_12305674:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,2,3,0,5,6,7,4]
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 2, i32 3, i32 0, i32 5, i32 6, i32 7, i32 4>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
Improve DAG combine pass on certain IR vector patterns
Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector
produced suboptimal code in AVX2 mode with certain IR combinations.
In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32
(undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical,
but then mysteriously generated rather bad code; the movq/movhpd combination
didn't match.
The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs
would get promoted to 4f32 by the type legalizer, eventually resulting
in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing
these were both half the output size, concatted them and then produced
a shuffle. However, the resulting concat + shuffle was more complex than
it should be; in the case where the upper half of the output is undef, we
probably want to generate shuffle + concat instead.
This enhancement causes the vector_shuffle combine step to recognize this
suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR
in case the same suboptimal pattern occurs for other reasons.
This results in the optimizer correctly producing the optimal movq + movhpd
sequence for all three variations on this IR, even with AVX2.
I've included a test case.
Radar link: rdar://problem/19287012
Fix for PR 21943.
From: Fiona Glaser <fglaser@apple.com>
llvm-svn: 226360
2015-01-17 09:35:56 +08:00
|
|
|
define <8x float> @concat_v2f32_1(<2 x float>* %tmp64, <2 x float>* %tmp65) {
|
|
|
|
; ALL-LABEL: concat_v2f32_1:
|
|
|
|
; ALL: # BB#0: # %entry
|
2015-01-31 22:09:36 +08:00
|
|
|
; ALL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
|
Improve DAG combine pass on certain IR vector patterns
Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector
produced suboptimal code in AVX2 mode with certain IR combinations.
In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32
(undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical,
but then mysteriously generated rather bad code; the movq/movhpd combination
didn't match.
The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs
would get promoted to 4f32 by the type legalizer, eventually resulting
in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing
these were both half the output size, concatted them and then produced
a shuffle. However, the resulting concat + shuffle was more complex than
it should be; in the case where the upper half of the output is undef, we
probably want to generate shuffle + concat instead.
This enhancement causes the vector_shuffle combine step to recognize this
suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR
in case the same suboptimal pattern occurs for other reasons.
This results in the optimizer correctly producing the optimal movq + movhpd
sequence for all three variations on this IR, even with AVX2.
I've included a test case.
Radar link: rdar://problem/19287012
Fix for PR 21943.
From: Fiona Glaser <fglaser@apple.com>
llvm-svn: 226360
2015-01-17 09:35:56 +08:00
|
|
|
; ALL-NEXT: vmovhpd (%rsi), %xmm0, %xmm0
|
|
|
|
; ALL-NEXT: retq
|
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp74 = load <2 x float>, <2 x float>* %tmp65, align 8
|
|
|
|
%tmp72 = load <2 x float>, <2 x float>* %tmp64, align 8
|
Improve DAG combine pass on certain IR vector patterns
Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector
produced suboptimal code in AVX2 mode with certain IR combinations.
In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32
(undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical,
but then mysteriously generated rather bad code; the movq/movhpd combination
didn't match.
The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs
would get promoted to 4f32 by the type legalizer, eventually resulting
in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing
these were both half the output size, concatted them and then produced
a shuffle. However, the resulting concat + shuffle was more complex than
it should be; in the case where the upper half of the output is undef, we
probably want to generate shuffle + concat instead.
This enhancement causes the vector_shuffle combine step to recognize this
suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR
in case the same suboptimal pattern occurs for other reasons.
This results in the optimizer correctly producing the optimal movq + movhpd
sequence for all three variations on this IR, even with AVX2.
I've included a test case.
Radar link: rdar://problem/19287012
Fix for PR 21943.
From: Fiona Glaser <fglaser@apple.com>
llvm-svn: 226360
2015-01-17 09:35:56 +08:00
|
|
|
%tmp73 = shufflevector <2 x float> %tmp72, <2 x float> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
|
|
|
%tmp75 = shufflevector <2 x float> %tmp74, <2 x float> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
|
|
|
%tmp76 = shufflevector <8 x float> %tmp73, <8 x float> %tmp75, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 undef>
|
|
|
|
ret <8 x float> %tmp76
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8x float> @concat_v2f32_2(<2 x float>* %tmp64, <2 x float>* %tmp65) {
|
|
|
|
; ALL-LABEL: concat_v2f32_2:
|
|
|
|
; ALL: # BB#0: # %entry
|
2015-01-31 22:09:36 +08:00
|
|
|
; ALL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
|
Improve DAG combine pass on certain IR vector patterns
Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector
produced suboptimal code in AVX2 mode with certain IR combinations.
In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32
(undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical,
but then mysteriously generated rather bad code; the movq/movhpd combination
didn't match.
The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs
would get promoted to 4f32 by the type legalizer, eventually resulting
in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing
these were both half the output size, concatted them and then produced
a shuffle. However, the resulting concat + shuffle was more complex than
it should be; in the case where the upper half of the output is undef, we
probably want to generate shuffle + concat instead.
This enhancement causes the vector_shuffle combine step to recognize this
suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR
in case the same suboptimal pattern occurs for other reasons.
This results in the optimizer correctly producing the optimal movq + movhpd
sequence for all three variations on this IR, even with AVX2.
I've included a test case.
Radar link: rdar://problem/19287012
Fix for PR 21943.
From: Fiona Glaser <fglaser@apple.com>
llvm-svn: 226360
2015-01-17 09:35:56 +08:00
|
|
|
; ALL-NEXT: vmovhpd (%rsi), %xmm0, %xmm0
|
|
|
|
; ALL-NEXT: retq
|
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp74 = load <2 x float>, <2 x float>* %tmp65, align 8
|
|
|
|
%tmp72 = load <2 x float>, <2 x float>* %tmp64, align 8
|
Improve DAG combine pass on certain IR vector patterns
Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector
produced suboptimal code in AVX2 mode with certain IR combinations.
In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32
(undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical,
but then mysteriously generated rather bad code; the movq/movhpd combination
didn't match.
The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs
would get promoted to 4f32 by the type legalizer, eventually resulting
in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing
these were both half the output size, concatted them and then produced
a shuffle. However, the resulting concat + shuffle was more complex than
it should be; in the case where the upper half of the output is undef, we
probably want to generate shuffle + concat instead.
This enhancement causes the vector_shuffle combine step to recognize this
suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR
in case the same suboptimal pattern occurs for other reasons.
This results in the optimizer correctly producing the optimal movq + movhpd
sequence for all three variations on this IR, even with AVX2.
I've included a test case.
Radar link: rdar://problem/19287012
Fix for PR 21943.
From: Fiona Glaser <fglaser@apple.com>
llvm-svn: 226360
2015-01-17 09:35:56 +08:00
|
|
|
%tmp76 = shufflevector <2 x float> %tmp72, <2 x float> %tmp74, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
|
|
|
ret <8 x float> %tmp76
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8x float> @concat_v2f32_3(<2 x float>* %tmp64, <2 x float>* %tmp65) {
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|
; ALL-LABEL: concat_v2f32_3:
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|
|
|
; ALL: # BB#0: # %entry
|
2015-01-31 22:09:36 +08:00
|
|
|
; ALL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
|
Improve DAG combine pass on certain IR vector patterns
Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector
produced suboptimal code in AVX2 mode with certain IR combinations.
In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32
(undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical,
but then mysteriously generated rather bad code; the movq/movhpd combination
didn't match.
The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs
would get promoted to 4f32 by the type legalizer, eventually resulting
in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing
these were both half the output size, concatted them and then produced
a shuffle. However, the resulting concat + shuffle was more complex than
it should be; in the case where the upper half of the output is undef, we
probably want to generate shuffle + concat instead.
This enhancement causes the vector_shuffle combine step to recognize this
suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR
in case the same suboptimal pattern occurs for other reasons.
This results in the optimizer correctly producing the optimal movq + movhpd
sequence for all three variations on this IR, even with AVX2.
I've included a test case.
Radar link: rdar://problem/19287012
Fix for PR 21943.
From: Fiona Glaser <fglaser@apple.com>
llvm-svn: 226360
2015-01-17 09:35:56 +08:00
|
|
|
; ALL-NEXT: vmovhpd (%rsi), %xmm0, %xmm0
|
|
|
|
; ALL-NEXT: retq
|
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp74 = load <2 x float>, <2 x float>* %tmp65, align 8
|
|
|
|
%tmp72 = load <2 x float>, <2 x float>* %tmp64, align 8
|
Improve DAG combine pass on certain IR vector patterns
Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector
produced suboptimal code in AVX2 mode with certain IR combinations.
In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32
(undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical,
but then mysteriously generated rather bad code; the movq/movhpd combination
didn't match.
The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs
would get promoted to 4f32 by the type legalizer, eventually resulting
in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing
these were both half the output size, concatted them and then produced
a shuffle. However, the resulting concat + shuffle was more complex than
it should be; in the case where the upper half of the output is undef, we
probably want to generate shuffle + concat instead.
This enhancement causes the vector_shuffle combine step to recognize this
suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR
in case the same suboptimal pattern occurs for other reasons.
This results in the optimizer correctly producing the optimal movq + movhpd
sequence for all three variations on this IR, even with AVX2.
I've included a test case.
Radar link: rdar://problem/19287012
Fix for PR 21943.
From: Fiona Glaser <fglaser@apple.com>
llvm-svn: 226360
2015-01-17 09:35:56 +08:00
|
|
|
%tmp76 = shufflevector <2 x float> %tmp72, <2 x float> %tmp74, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
%res = shufflevector <4 x float> %tmp76, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
|
|
|
ret <8 x float> %res
|
|
|
|
}
|
2015-04-01 02:43:43 +08:00
|
|
|
|
|
|
|
define <8 x i32> @insert_mem_and_zero_v8i32(i32* %ptr) {
|
2015-06-24 08:03:48 +08:00
|
|
|
; ALL-LABEL: insert_mem_and_zero_v8i32:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
; ALL-NEXT: retq
|
2015-04-01 02:43:43 +08:00
|
|
|
%a = load i32, i32* %ptr
|
|
|
|
%v = insertelement <8 x i32> undef, i32 %a, i32 0
|
|
|
|
%shuffle = shufflevector <8 x i32> %v, <8 x i32> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
|
|
|
ret <8 x i32> %shuffle
|
|
|
|
}
|
|
|
|
|
2015-08-19 04:51:15 +08:00
|
|
|
define <8 x i32> @concat_v8i32_0123CDEF(<8 x i32> %a, <8 x i32> %b) {
|
2015-08-20 04:09:50 +08:00
|
|
|
; AVX1-LABEL: concat_v8i32_0123CDEF:
|
|
|
|
; AVX1: # BB#0:
|
|
|
|
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: concat_v8i32_0123CDEF:
|
|
|
|
; AVX2: # BB#0:
|
|
|
|
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
|
|
|
|
; AVX2-NEXT: retq
|
2015-08-19 04:51:15 +08:00
|
|
|
%alo = shufflevector <8 x i32> %a, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
%bhi = shufflevector <8 x i32> %b, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
|
|
|
%shuf = shufflevector <4 x i32> %alo, <4 x i32> %bhi, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
ret <8 x i32> %shuf
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @concat_v8i32_4567CDEF_bc(<8 x i32> %a0, <8 x i32> %a1) {
|
|
|
|
; ALL-LABEL: concat_v8i32_4567CDEF_bc:
|
|
|
|
; ALL: # BB#0:
|
2015-08-20 04:09:50 +08:00
|
|
|
; ALL-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
|
2015-08-19 04:51:15 +08:00
|
|
|
; ALL-NEXT: retq
|
|
|
|
%a0hi = shufflevector <8 x i32> %a0, <8 x i32> %a1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
|
|
|
%a1hi = shufflevector <8 x i32> %a0, <8 x i32> %a1, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
|
|
|
|
%bc0hi = bitcast <4 x i32> %a0hi to <2 x i64>
|
|
|
|
%bc1hi = bitcast <4 x i32> %a1hi to <2 x i64>
|
|
|
|
%shuffle64 = shufflevector <2 x i64> %bc0hi, <2 x i64> %bc1hi, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
%shuffle32 = bitcast <4 x i64> %shuffle64 to <8 x i32>
|
|
|
|
ret <8 x i32> %shuffle32
|
|
|
|
}
|
2015-08-21 04:59:41 +08:00
|
|
|
|
2015-08-23 23:22:14 +08:00
|
|
|
define <8 x float> @concat_v8f32_4567CDEF_bc(<8 x float> %f0, <8 x float> %f1) {
|
|
|
|
; ALL-LABEL: concat_v8f32_4567CDEF_bc:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
|
|
|
|
; ALL-NEXT: retq
|
|
|
|
%a0 = bitcast <8 x float> %f0 to <4 x i64>
|
|
|
|
%a1 = bitcast <8 x float> %f1 to <8 x i32>
|
|
|
|
%a0hi = shufflevector <4 x i64> %a0, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
|
|
|
|
%a1hi = shufflevector <8 x i32> %a1, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
|
|
|
%bc0hi = bitcast <2 x i64> %a0hi to <2 x i64>
|
|
|
|
%bc1hi = bitcast <4 x i32> %a1hi to <2 x i64>
|
|
|
|
%shuffle64 = shufflevector <2 x i64> %bc0hi, <2 x i64> %bc1hi, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
%shuffle32 = bitcast <4 x i64> %shuffle64 to <8 x float>
|
|
|
|
ret <8 x float> %shuffle32
|
|
|
|
}
|
|
|
|
|
2015-08-21 04:59:41 +08:00
|
|
|
define <8 x i32> @insert_dup_mem_v8i32(i32* %ptr) {
|
|
|
|
; ALL-LABEL: insert_dup_mem_v8i32:
|
|
|
|
; ALL: # BB#0:
|
|
|
|
; ALL-NEXT: vbroadcastss (%rdi), %ymm0
|
|
|
|
; ALL-NEXT: retq
|
|
|
|
%tmp = load i32, i32* %ptr, align 4
|
|
|
|
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %tmp, i32 0
|
|
|
|
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <8 x i32> zeroinitializer
|
|
|
|
ret <8 x i32> %tmp2
|
|
|
|
}
|