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llvm-project/llvm/test/CodeGen/X86/rtm.ll

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[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets. llvm-svn: 297518
2017-03-11 05:55:24 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Fix PR33028 - '-verify-mahcineinstrs' starts to complain allocatable live-in physical registers on non-entry or non-landing-pad basic blocks. - Refactor the XBEGIN translation to define EAX on a dedicated fallback code path due to XABORT. Add a pseudo instruction to define EAX explicitly to avoid add physical register live-in. Differential Revision: https://reviews.llvm.org/D33168 llvm-svn: 303306
2017-05-18 05:48:00 +08:00
; RUN: llc -verify-machineinstrs < %s -mtriple=i686-unknown-unknown -mattr=+rtm | FileCheck %s --check-prefix=X86
; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown -mattr=+rtm | FileCheck %s --check-prefix=X64
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
declare i32 @llvm.x86.xbegin() nounwind
declare void @llvm.x86.xend() nounwind
[X86][RTM] _xabort() should not have "noreturn" attribute Differential Revision: http://reviews.llvm.org/D20518 llvm-svn: 270437
2016-05-23 22:04:17 +08:00
declare void @llvm.x86.xabort(i8) nounwind
declare void @f1()
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
define i32 @test_xbegin() nounwind uwtable {
[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets. llvm-svn: 297518
2017-03-11 05:55:24 +08:00
; X86-LABEL: test_xbegin:
; X86: # BB#0: # %entry
; X86-NEXT: xbegin .LBB0_2
; X86-NEXT: # BB#1: # %entry
; X86-NEXT: movl $-1, %eax
Fix PR33028 - '-verify-mahcineinstrs' starts to complain allocatable live-in physical registers on non-entry or non-landing-pad basic blocks. - Refactor the XBEGIN translation to define EAX on a dedicated fallback code path due to XABORT. Add a pseudo instruction to define EAX explicitly to avoid add physical register live-in. Differential Revision: https://reviews.llvm.org/D33168 llvm-svn: 303306
2017-05-18 05:48:00 +08:00
; X86: .LBB0_2: # %entry
; X86-NEXT: # XABORT DEF
[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets. llvm-svn: 297518
2017-03-11 05:55:24 +08:00
; X86-NEXT: retl
;
; X64-LABEL: test_xbegin:
; X64: # BB#0: # %entry
; X64-NEXT: xbegin .LBB0_2
; X64-NEXT: # BB#1: # %entry
; X64-NEXT: movl $-1, %eax
Fix PR33028 - '-verify-mahcineinstrs' starts to complain allocatable live-in physical registers on non-entry or non-landing-pad basic blocks. - Refactor the XBEGIN translation to define EAX on a dedicated fallback code path due to XABORT. Add a pseudo instruction to define EAX explicitly to avoid add physical register live-in. Differential Revision: https://reviews.llvm.org/D33168 llvm-svn: 303306
2017-05-18 05:48:00 +08:00
; X64: .LBB0_2: # %entry
; X64-NEXT: # XABORT DEF
[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets. llvm-svn: 297518
2017-03-11 05:55:24 +08:00
; X64-NEXT: retq
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
entry:
%0 = tail call i32 @llvm.x86.xbegin() nounwind
ret i32 %0
}
define void @test_xend() nounwind uwtable {
[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets. llvm-svn: 297518
2017-03-11 05:55:24 +08:00
; X86-LABEL: test_xend:
; X86: # BB#0: # %entry
; X86-NEXT: xend
; X86-NEXT: retl
;
; X64-LABEL: test_xend:
; X64: # BB#0: # %entry
; X64-NEXT: xend
; X64-NEXT: retq
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
entry:
tail call void @llvm.x86.xend() nounwind
ret void
}
define void @test_xabort() nounwind uwtable {
[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets. llvm-svn: 297518
2017-03-11 05:55:24 +08:00
; X86-LABEL: test_xabort:
; X86: # BB#0: # %entry
; X86-NEXT: xabort $2
; X86-NEXT: retl
;
; X64-LABEL: test_xabort:
; X64: # BB#0: # %entry
; X64-NEXT: xabort $2
; X64-NEXT: retq
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
entry:
tail call void @llvm.x86.xabort(i8 2)
[X86][RTM] _xabort() should not have "noreturn" attribute Differential Revision: http://reviews.llvm.org/D20518 llvm-svn: 270437
2016-05-23 22:04:17 +08:00
ret void
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
}
[X86][RTM] _xabort() should not have "noreturn" attribute Differential Revision: http://reviews.llvm.org/D20518 llvm-svn: 270437
2016-05-23 22:04:17 +08:00
define void @f2(i32 %x) nounwind uwtable {
[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets. llvm-svn: 297518
2017-03-11 05:55:24 +08:00
; X86-LABEL: f2:
; X86: # BB#0: # %entry
; X86-NEXT: xabort $1
; X86-NEXT: calll f1
; X86-NEXT: retl
;
; X64-LABEL: f2:
; X64: # BB#0: # %entry
; X64-NEXT: pushq %rax
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; X64-NEXT: xabort $1
; X64-NEXT: callq f1
; X64-NEXT: popq %rax
Reland "Correct dwarf unwind information in function epilogue for X86" Reland r317100 with minor fix regarding ComputeCommonTailLength function in BranchFolding.cpp. Skipping top CFI instructions block needs to executed on several more return points in ComputeCommonTailLength(). Original r317100 message: "Correct dwarf unwind information in function epilogue for X86" This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: - CFI instructions do not affect code generation - Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Changed CFI instructions so that they: - are duplicable - are not counted as instructions when tail duplicating or tail merging - can be compared as equal Added CFIInstrInserter pass: - analyzes each basic block to determine cfa offset and register valid at its entry and exit - verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors - inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. llvm-svn: 317579
2017-11-07 22:40:27 +08:00
; X64-NEXT: .cfi_def_cfa_offset 8
[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets. llvm-svn: 297518
2017-03-11 05:55:24 +08:00
; X64-NEXT: retq
[X86][RTM] _xabort() should not have "noreturn" attribute Differential Revision: http://reviews.llvm.org/D20518 llvm-svn: 270437
2016-05-23 22:04:17 +08:00
entry:
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
call void @llvm.x86.xabort(i8 1)
call void @f1()
ret void
}
[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets. llvm-svn: 297518
2017-03-11 05:55:24 +08:00