Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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//===- AMDGPUInstructionSelector.cpp ----------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the InstructionSelector class for
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/// AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstructionSelector.h"
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPURegisterBankInfo.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
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#include "AMDGPUTargetMachine.h"
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AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
Summary:
MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction
and register defintions, which are huge so we only want to include
them where needed.
This will also make it easier if we want to split the R600 and GCN
definitions into separate tablegenerated files.
I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h
because it uses some enums from the header to initialize default values
for the SIMachineFunction class, so I ended up having to remove includes of
SIMachineFunctionInfo.h from headers too.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46272
llvm-svn: 332930
2018-05-22 10:03:23 +08:00
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
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2018-01-18 03:31:33 +08:00
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "amdgpu-isel"
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using namespace llvm;
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|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
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#define GET_GLOBALISEL_IMPL
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_IMPL
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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AMDGPUInstructionSelector::AMDGPUInstructionSelector(
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AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
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const SISubtarget &STI, const AMDGPURegisterBankInfo &RBI,
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const AMDGPUTargetMachine &TM)
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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: InstructionSelector(), TII(*STI.getInstrInfo()),
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AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
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TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
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STI(STI),
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EnableLateStructurizeCFG(AMDGPUTargetMachine::EnableLateStructurizeCFG),
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#define GET_GLOBALISEL_PREDICATES_INIT
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_INIT
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#define GET_GLOBALISEL_TEMPORARIES_INIT
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_INIT
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,AMDGPUASI(STI.getAMDGPUAS())
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{
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}
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const char *AMDGPUInstructionSelector::getName() { return DEBUG_TYPE; }
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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2018-05-11 05:20:10 +08:00
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bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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I.setDesc(TII.get(TargetOpcode::COPY));
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for (const MachineOperand &MO : I.operands()) {
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if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
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continue;
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const TargetRegisterClass *RC =
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TRI.getConstrainedRegClassForOperand(MO, MRI);
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if (!RC)
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continue;
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RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
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}
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return true;
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}
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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MachineOperand
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AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
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unsigned SubIdx) const {
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MachineInstr *MI = MO.getParent();
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MachineBasicBlock *BB = MO.getParent()->getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned DstReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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if (MO.isReg()) {
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unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx);
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unsigned Reg = MO.getReg();
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BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
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.addReg(Reg, 0, ComposedSubIdx);
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return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
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MO.isKill(), MO.isDead(), MO.isUndef(),
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MO.isEarlyClobber(), 0, MO.isDebug(),
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MO.isInternalRead());
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}
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assert(MO.isImm());
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APInt Imm(64, MO.getImm());
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switch (SubIdx) {
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default:
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llvm_unreachable("do not know to split immediate with this sub index.");
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case AMDGPU::sub0:
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return MachineOperand::CreateImm(Imm.getLoBits(32).getSExtValue());
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case AMDGPU::sub1:
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return MachineOperand::CreateImm(Imm.getHiBits(32).getSExtValue());
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}
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}
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bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned Size = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
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unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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if (Size != 64)
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return false;
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DebugLoc DL = I.getDebugLoc();
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2017-01-31 23:24:11 +08:00
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MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
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MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
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|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
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2017-01-31 23:24:11 +08:00
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.add(Lo1)
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.add(Lo2);
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MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
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MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
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2017-01-31 23:24:11 +08:00
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.add(Hi1)
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.add(Hi2);
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
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.addReg(DstLo)
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.addImm(AMDGPU::sub0)
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.addReg(DstHi)
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.addImm(AMDGPU::sub1);
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for (MachineOperand &MO : I.explicit_operands()) {
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if (!MO.isReg() || TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
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continue;
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RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI);
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}
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I.eraseFromParent();
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return true;
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}
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bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
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return selectG_ADD(I);
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}
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bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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2018-05-12 07:12:49 +08:00
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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DebugLoc DL = I.getDebugLoc();
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2018-05-12 07:12:49 +08:00
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unsigned StoreSize = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
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unsigned Opcode;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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// FIXME: Select store instruction based on address space
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2018-05-12 07:12:49 +08:00
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switch (StoreSize) {
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default:
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return false;
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case 32:
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Opcode = AMDGPU::FLAT_STORE_DWORD;
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break;
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case 64:
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Opcode = AMDGPU::FLAT_STORE_DWORDX2;
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break;
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case 96:
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Opcode = AMDGPU::FLAT_STORE_DWORDX3;
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break;
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case 128:
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Opcode = AMDGPU::FLAT_STORE_DWORDX4;
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break;
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}
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MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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.add(I.getOperand(1))
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.add(I.getOperand(0))
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2017-06-12 23:55:58 +08:00
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.addImm(0) // offset
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.addImm(0) // glc
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.addImm(0); // slc
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
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2017-05-12 01:38:33 +08:00
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|
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
// Now that we selected an opcode, we need to constrain the register
|
|
|
|
// operands to use appropriate classes.
|
|
|
|
bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
|
|
|
|
|
|
|
|
I.eraseFromParent();
|
|
|
|
return Ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
|
|
|
|
MachineBasicBlock *BB = I.getParent();
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
2018-05-16 01:57:09 +08:00
|
|
|
MachineOperand &ImmOp = I.getOperand(1);
|
|
|
|
|
|
|
|
// The AMDGPU backend only supports Imm operands and not CImm or FPImm.
|
|
|
|
if (ImmOp.isFPImm()) {
|
|
|
|
const APInt &Imm = ImmOp.getFPImm()->getValueAPF().bitcastToAPInt();
|
|
|
|
ImmOp.ChangeToImmediate(Imm.getZExtValue());
|
|
|
|
} else if (ImmOp.isCImm()) {
|
|
|
|
ImmOp.ChangeToImmediate(ImmOp.getCImm()->getZExtValue());
|
|
|
|
}
|
|
|
|
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
unsigned DstReg = I.getOperand(0).getReg();
|
2018-05-16 01:57:09 +08:00
|
|
|
unsigned Size;
|
|
|
|
bool IsSgpr;
|
|
|
|
const RegisterBank *RB = MRI.getRegBankOrNull(I.getOperand(0).getReg());
|
|
|
|
if (RB) {
|
|
|
|
IsSgpr = RB->getID() == AMDGPU::SGPRRegBankID;
|
|
|
|
Size = MRI.getType(DstReg).getSizeInBits();
|
|
|
|
} else {
|
|
|
|
const TargetRegisterClass *RC = TRI.getRegClassForReg(MRI, DstReg);
|
|
|
|
IsSgpr = TRI.isSGPRClass(RC);
|
2018-05-22 01:49:31 +08:00
|
|
|
Size = TRI.getRegSizeInBits(*RC);
|
2018-05-16 01:57:09 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (Size != 32 && Size != 64)
|
|
|
|
return false;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
|
2018-05-16 01:57:09 +08:00
|
|
|
unsigned Opcode = IsSgpr ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
if (Size == 32) {
|
2018-05-16 01:57:09 +08:00
|
|
|
I.setDesc(TII.get(Opcode));
|
|
|
|
I.addImplicitDefUseOperands(*MF);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
|
|
|
|
}
|
|
|
|
|
|
|
|
DebugLoc DL = I.getDebugLoc();
|
2018-05-16 01:57:09 +08:00
|
|
|
const TargetRegisterClass *RC = IsSgpr ? &AMDGPU::SReg_32_XM0RegClass :
|
|
|
|
&AMDGPU::VGPR_32RegClass;
|
|
|
|
unsigned LoReg = MRI.createVirtualRegister(RC);
|
|
|
|
unsigned HiReg = MRI.createVirtualRegister(RC);
|
|
|
|
const APInt &Imm = APInt(Size, I.getOperand(1).getImm());
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
|
2018-05-16 01:57:09 +08:00
|
|
|
BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg)
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
.addImm(Imm.trunc(32).getZExtValue());
|
|
|
|
|
2018-05-16 01:57:09 +08:00
|
|
|
BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg)
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
.addImm(Imm.ashr(32).getZExtValue());
|
|
|
|
|
2018-05-16 01:57:09 +08:00
|
|
|
const MachineInstr *RS =
|
|
|
|
BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
|
|
|
|
.addReg(LoReg)
|
|
|
|
.addImm(AMDGPU::sub0)
|
|
|
|
.addReg(HiReg)
|
|
|
|
.addImm(AMDGPU::sub1);
|
|
|
|
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
// We can't call constrainSelectedInstRegOperands here, because it doesn't
|
|
|
|
// work for target independent opcodes
|
|
|
|
I.eraseFromParent();
|
2018-05-16 01:57:09 +08:00
|
|
|
const TargetRegisterClass *DstRC =
|
|
|
|
TRI.getConstrainedRegClassForOperand(RS->getOperand(0), MRI);
|
|
|
|
if (!DstRC)
|
|
|
|
return true;
|
|
|
|
return RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool isConstant(const MachineInstr &MI) {
|
|
|
|
return MI.getOpcode() == TargetOpcode::G_CONSTANT;
|
|
|
|
}
|
|
|
|
|
|
|
|
void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load,
|
|
|
|
const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const {
|
|
|
|
|
|
|
|
const MachineInstr *PtrMI = MRI.getUniqueVRegDef(Load.getOperand(1).getReg());
|
|
|
|
|
|
|
|
assert(PtrMI);
|
|
|
|
|
|
|
|
if (PtrMI->getOpcode() != TargetOpcode::G_GEP)
|
|
|
|
return;
|
|
|
|
|
|
|
|
GEPInfo GEPInfo(*PtrMI);
|
|
|
|
|
|
|
|
for (unsigned i = 1, e = 3; i < e; ++i) {
|
|
|
|
const MachineOperand &GEPOp = PtrMI->getOperand(i);
|
|
|
|
const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());
|
|
|
|
assert(OpDef);
|
|
|
|
if (isConstant(*OpDef)) {
|
|
|
|
// FIXME: Is it possible to have multiple Imm parts? Maybe if we
|
|
|
|
// are lacking other optimizations.
|
|
|
|
assert(GEPInfo.Imm == 0);
|
|
|
|
GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue();
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI);
|
|
|
|
if (OpBank->getID() == AMDGPU::SGPRRegBankID)
|
|
|
|
GEPInfo.SgprParts.push_back(GEPOp.getReg());
|
|
|
|
else
|
|
|
|
GEPInfo.VgprParts.push_back(GEPOp.getReg());
|
|
|
|
}
|
|
|
|
|
|
|
|
AddrInfo.push_back(GEPInfo);
|
|
|
|
getAddrModeInfo(*PtrMI, MRI, AddrInfo);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool isInstrUniform(const MachineInstr &MI) {
|
|
|
|
if (!MI.hasOneMemOperand())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
const MachineMemOperand *MMO = *MI.memoperands_begin();
|
|
|
|
const Value *Ptr = MMO->getValue();
|
|
|
|
|
|
|
|
// UndefValue means this is a load of a kernel input. These are uniform.
|
|
|
|
// Sometimes LDS instructions have constant pointers.
|
|
|
|
// If Ptr is null, then that means this mem operand contains a
|
|
|
|
// PseudoSourceValue like GOT.
|
|
|
|
if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
|
|
|
|
isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
|
|
|
|
return true;
|
|
|
|
|
2018-02-10 00:57:57 +08:00
|
|
|
if (MMO->getAddrSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
|
|
|
|
return true;
|
|
|
|
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
const Instruction *I = dyn_cast<Instruction>(Ptr);
|
|
|
|
return I && I->getMetadata("amdgpu.uniform");
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned getSmrdOpcode(unsigned BaseOpcode, unsigned LoadSize) {
|
|
|
|
|
|
|
|
if (LoadSize == 32)
|
|
|
|
return BaseOpcode;
|
|
|
|
|
|
|
|
switch (BaseOpcode) {
|
|
|
|
case AMDGPU::S_LOAD_DWORD_IMM:
|
|
|
|
switch (LoadSize) {
|
|
|
|
case 64:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX2_IMM;
|
|
|
|
case 128:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX4_IMM;
|
|
|
|
case 256:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX8_IMM;
|
|
|
|
case 512:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX16_IMM;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case AMDGPU::S_LOAD_DWORD_IMM_ci:
|
|
|
|
switch (LoadSize) {
|
|
|
|
case 64:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX2_IMM_ci;
|
|
|
|
case 128:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX4_IMM_ci;
|
|
|
|
case 256:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX8_IMM_ci;
|
|
|
|
case 512:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX16_IMM_ci;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case AMDGPU::S_LOAD_DWORD_SGPR:
|
|
|
|
switch (LoadSize) {
|
|
|
|
case 64:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX2_SGPR;
|
|
|
|
case 128:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX4_SGPR;
|
|
|
|
case 256:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX8_SGPR;
|
|
|
|
case 512:
|
|
|
|
return AMDGPU::S_LOAD_DWORDX16_SGPR;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
llvm_unreachable("Invalid base smrd opcode or size");
|
|
|
|
}
|
|
|
|
|
|
|
|
bool AMDGPUInstructionSelector::hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const {
|
|
|
|
for (const GEPInfo &GEPInfo : AddrInfo) {
|
|
|
|
if (!GEPInfo.VgprParts.empty())
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool AMDGPUInstructionSelector::selectSMRD(MachineInstr &I,
|
|
|
|
ArrayRef<GEPInfo> AddrInfo) const {
|
|
|
|
|
|
|
|
if (!I.hasOneMemOperand())
|
|
|
|
return false;
|
|
|
|
|
2018-02-10 00:57:57 +08:00
|
|
|
if ((*I.memoperands_begin())->getAddrSpace() != AMDGPUASI.CONSTANT_ADDRESS &&
|
|
|
|
(*I.memoperands_begin())->getAddrSpace() != AMDGPUASI.CONSTANT_ADDRESS_32BIT)
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!isInstrUniform(I))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (hasVgprParts(AddrInfo))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MachineBasicBlock *BB = I.getParent();
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
const SISubtarget &Subtarget = MF->getSubtarget<SISubtarget>();
|
|
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
|
|
unsigned DstReg = I.getOperand(0).getReg();
|
|
|
|
const DebugLoc &DL = I.getDebugLoc();
|
|
|
|
unsigned Opcode;
|
|
|
|
unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
|
|
|
|
|
|
|
|
if (!AddrInfo.empty() && AddrInfo[0].SgprParts.size() == 1) {
|
|
|
|
|
|
|
|
const GEPInfo &GEPInfo = AddrInfo[0];
|
|
|
|
|
|
|
|
unsigned PtrReg = GEPInfo.SgprParts[0];
|
|
|
|
int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(Subtarget, GEPInfo.Imm);
|
|
|
|
if (AMDGPU::isLegalSMRDImmOffset(Subtarget, GEPInfo.Imm)) {
|
|
|
|
Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM, LoadSize);
|
|
|
|
|
|
|
|
MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
|
|
|
|
.addReg(PtrReg)
|
|
|
|
.addImm(EncodedImm)
|
|
|
|
.addImm(0); // glc
|
|
|
|
return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Subtarget.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS &&
|
|
|
|
isUInt<32>(EncodedImm)) {
|
|
|
|
Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM_ci, LoadSize);
|
|
|
|
MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
|
|
|
|
.addReg(PtrReg)
|
|
|
|
.addImm(EncodedImm)
|
|
|
|
.addImm(0); // glc
|
|
|
|
return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (isUInt<32>(GEPInfo.Imm)) {
|
|
|
|
Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_SGPR, LoadSize);
|
|
|
|
unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
|
|
|
|
BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), OffsetReg)
|
|
|
|
.addImm(GEPInfo.Imm);
|
|
|
|
|
|
|
|
MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
|
|
|
|
.addReg(PtrReg)
|
|
|
|
.addReg(OffsetReg)
|
|
|
|
.addImm(0); // glc
|
|
|
|
return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned PtrReg = I.getOperand(1).getReg();
|
|
|
|
Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM, LoadSize);
|
|
|
|
MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg)
|
|
|
|
.addReg(PtrReg)
|
|
|
|
.addImm(0)
|
|
|
|
.addImm(0); // glc
|
|
|
|
return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const {
|
|
|
|
MachineBasicBlock *BB = I.getParent();
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
|
|
DebugLoc DL = I.getDebugLoc();
|
|
|
|
unsigned DstReg = I.getOperand(0).getReg();
|
|
|
|
unsigned PtrReg = I.getOperand(1).getReg();
|
|
|
|
unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
|
|
|
|
unsigned Opcode;
|
|
|
|
|
|
|
|
SmallVector<GEPInfo, 4> AddrInfo;
|
|
|
|
|
|
|
|
getAddrModeInfo(I, MRI, AddrInfo);
|
|
|
|
|
|
|
|
if (selectSMRD(I, AddrInfo)) {
|
|
|
|
I.eraseFromParent();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (LoadSize) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Load size not supported\n");
|
|
|
|
case 32:
|
|
|
|
Opcode = AMDGPU::FLAT_LOAD_DWORD;
|
|
|
|
break;
|
|
|
|
case 64:
|
|
|
|
Opcode = AMDGPU::FLAT_LOAD_DWORDX2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
|
|
|
|
.add(I.getOperand(0))
|
|
|
|
.addReg(PtrReg)
|
2017-06-12 23:55:58 +08:00
|
|
|
.addImm(0) // offset
|
|
|
|
.addImm(0) // glc
|
|
|
|
.addImm(0); // slc
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
|
|
|
|
bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
|
|
|
|
I.eraseFromParent();
|
|
|
|
return Ret;
|
|
|
|
}
|
|
|
|
|
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules
Summary:
This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV,
causes TableGen to instrument the generated table to collect rule coverage
information. However, LLVM_ENABLE_GISEL_COV goes a bit further than
LLVM_ENABLE_DAGISEL_COV. The information is written to files
(${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be
concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will
read this information and use it to emit warnings about untested rules.
This technique could also be used by SelectionDAG and can be further
extended to detect hot rules and give them priority over colder rules.
Usage:
* Enable LLVM_ENABLE_GISEL_COV in CMake
* Build the compiler and run some tests
* cat gisel-coverage-[0-9]* > gisel-coverage-all
* Delete lib/Target/*/*GenGlobalISel.inc*
* Build the compiler
Known issues:
* ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual
step due to a lack of a portable 'cat' command. It should be the
concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files.
* There's no mechanism to discard coverage information when the ruleset
changes
Depends on D39742
Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka
Reviewed By: rovka
Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D39747
llvm-svn: 318356
2017-11-16 08:46:35 +08:00
|
|
|
bool AMDGPUInstructionSelector::select(MachineInstr &I,
|
|
|
|
CodeGenCoverage &CoverageInfo) const {
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
|
|
|
|
if (!isPreISelGenericOpcode(I.getOpcode()))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
switch (I.getOpcode()) {
|
|
|
|
default:
|
|
|
|
break;
|
2018-05-11 13:44:16 +08:00
|
|
|
case TargetOpcode::G_FPTOUI:
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
|
|
case TargetOpcode::G_OR:
|
|
|
|
return selectImpl(I, CoverageInfo);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
case TargetOpcode::G_ADD:
|
|
|
|
return selectG_ADD(I);
|
2018-05-11 05:20:10 +08:00
|
|
|
case TargetOpcode::G_BITCAST:
|
|
|
|
return selectCOPY(I);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
case TargetOpcode::G_CONSTANT:
|
2018-05-16 01:57:09 +08:00
|
|
|
case TargetOpcode::G_FCONSTANT:
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-31 05:56:46 +08:00
|
|
|
return selectG_CONSTANT(I);
|
|
|
|
case TargetOpcode::G_GEP:
|
|
|
|
return selectG_GEP(I);
|
|
|
|
case TargetOpcode::G_LOAD:
|
|
|
|
return selectG_LOAD(I);
|
|
|
|
case TargetOpcode::G_STORE:
|
|
|
|
return selectG_STORE(I);
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
|
|
|
|
|
|
///
|
|
|
|
/// This will select either an SGPR or VGPR operand and will save us from
|
|
|
|
/// having to write an extra tablegen pattern.
|
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
AMDGPUInstructionSelector::selectVSRC0(MachineOperand &Root) const {
|
|
|
|
return {{
|
|
|
|
[=](MachineInstrBuilder &MIB) { MIB.add(Root); }
|
|
|
|
}};
|
|
|
|
}
|
2018-05-11 13:44:16 +08:00
|
|
|
|
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
|
|
|
|
return {{
|
|
|
|
[=](MachineInstrBuilder &MIB) { MIB.add(Root); },
|
|
|
|
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src0_mods
|
|
|
|
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
|
|
|
|
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
|
|
|
|
}};
|
|
|
|
}
|