maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

2625 lines
95 KiB
C++
Raw Normal View History

[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file is part of the Mips Disassembler.
//
//===----------------------------------------------------------------------===//
[Mips] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 309993
2017-08-04 06:12:30 +08:00
#include "MCTargetDesc/MipsMCTargetDesc.h"
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
#include "Mips.h"
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
#include "llvm/ADT/ArrayRef.h"
[MC] Require an MCContext when constructing an MCDisassembler. This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
2014-04-15 12:40:56 +08:00
#include "llvm/MC/MCContext.h"
Reflect the MC/MCDisassembler split on the include/ level. No functional change, just moving code around. llvm-svn: 258818
2016-01-27 00:44:37 +08:00
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
#include "llvm/MC/MCFixedLenDisassembler.h"
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
#include "llvm/MC/MCInst.h"
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
#include "llvm/MC/MCRegisterInfo.h"
Sort the remaining #include lines in include/... and lib/.... I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
2017-06-06 19:49:48 +08:00
#include "llvm/MC/MCSubtargetInfo.h"
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
#include "llvm/Support/MathExtras.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "llvm/Support/TargetRegistry.h"
Sort the remaining #include lines in include/... and lib/.... I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
2017-06-06 19:49:48 +08:00
#include "llvm/Support/raw_ostream.h"
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
#include <cassert>
#include <cstdint>
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
using namespace llvm;
[Modules] Make Support/Debug.h modular. This requires it to not change behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. llvm-svn: 206822
2014-04-22 06:55:11 +08:00
#define DEBUG_TYPE "mips-disassembler"
[Mips] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 309993
2017-08-04 06:12:30 +08:00
using DecodeStatus = MCDisassembler::DecodeStatus;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Move MipsDisassembler classes into an anonymous namespace. llvm-svn: 155915
2012-05-01 22:34:24 +08:00
namespace {
[mips] Merge disassemblers into a single implementation. Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
2015-02-11 19:28:56 +08:00
class MipsDisassembler : public MCDisassembler {
bool IsMicroMips;
bool IsBigEndian;
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
public:
[mips] Merge disassemblers into a single implementation. Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
2015-02-11 19:28:56 +08:00
MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
: MCDisassembler(STI, Ctx),
Use std::bitset for SubtargetFeatures. Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
2015-05-26 18:47:10 +08:00
IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
IsBigEndian(IsBigEndian) {}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
[mips][atomics] Fix atomic instruction descriptions and uses. PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
2016-06-14 19:29:28 +08:00
bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
Use std::bitset for SubtargetFeatures. Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
2015-05-26 18:47:10 +08:00
bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
[mips] Add cache and pref instructions Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
2014-06-13 21:15:59 +08:00
bool hasMips32r6() const {
Use std::bitset for SubtargetFeatures. Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
2015-05-26 18:47:10 +08:00
return STI.getFeatureBits()[Mips::FeatureMips32r6];
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
}
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
[mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions Differential Revision: http://reviews.llvm.org/D17334 llvm-svn: 265002
2016-03-31 16:51:24 +08:00
bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
Use std::bitset for SubtargetFeatures. Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
2015-05-26 18:47:10 +08:00
bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
[mips][atomics] Fix atomic instruction descriptions and uses. PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
2016-06-14 19:29:28 +08:00
bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
[mips] Add new format for dmtc2/dmfc2 for Octeon CPUs. Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1. I had to introduce a new deconding namespace to avoid a decoding conflict. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D10083 llvm-svn: 238439
2015-05-29 00:23:16 +08:00
bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
[mips] Add cache and pref instructions Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
2014-06-13 21:15:59 +08:00
bool hasCOP3() const {
// Only present in MIPS-I and MIPS-II
return !hasMips32() && !hasMips3();
}
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Pass an ArrayRef to MCDisassembler::getInstruction. With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
2014-11-12 10:04:27 +08:00
ArrayRef<uint8_t> Bytes, uint64_t Address,
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
raw_ostream &VStream,
raw_ostream &CStream) const override;
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
};
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Move MipsDisassembler classes into an anonymous namespace. llvm-svn: 155915
2012-05-01 22:34:24 +08:00
} // end anonymous namespace
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
// Forward declare these because the autogenerated code will reference them.
// Definitions are further down.
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Remove the form field from Mips16 instruction formats and set things up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. llvm-svn: 175126
2013-02-14 11:05:25 +08:00
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement microMIPS 16-bit instructions registers Differential Revision: http://reviews.llvm.org/D5116 llvm-svn: 220273
2014-10-21 16:23:11 +08:00
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0 Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17. Differential Revision: http://reviews.llvm.org/D5780 llvm-svn: 222652
2014-11-24 22:25:53 +08:00
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions. Also, fix predicates. llvm-svn: 189432
2013-08-28 08:55:15 +08:00
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips] Rename DSPRegs. llvm-svn: 188342
2013-08-14 08:53:38 +08:00
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
MIPS DSP: add functions which decode DSP and accumulator registers. llvm-svn: 164748
2012-09-27 10:01:10 +08:00
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] Fix FP branch instructions to have explicit FP condition code register operands. llvm-svn: 187238
2013-07-27 04:13:47 +08:00
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
MIPS DSP: add functions which decode DSP and accumulator registers. llvm-svn: 164748
2012-09-27 10:01:10 +08:00
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips][msa] Direct Object Emission support for the MSA instruction set. In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
2013-09-26 07:50:44 +08:00
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
2013-10-21 20:26:50 +08:00
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips][mips64r6] Add bc[12](eq|ne)z Summary: Depends on D3691 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3760 llvm-svn: 209292
2014-05-21 20:56:39 +08:00
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeBranchTarget(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and MULSAQ_S.W.PH instructions Differential Revision: http://reviews.llvm.org/D14117 llvm-svn: 269408
2016-05-13 19:32:53 +08:00
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement BEQZC and BNEZC instructions Differential Revision: http://reviews.llvm.org/D15417 llvm-svn: 269755
2016-05-17 19:10:15 +08:00
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions Differential Revision: http://reviews.llvm.org/D5271 llvm-svn: 225627
2015-01-12 20:03:34 +08:00
// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
// shifted left by 1 bit.
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226657
2015-01-21 20:39:30 +08:00
// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
// shifted left by 1 bit.
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
Support for microMIPS branch instructions. llvm-svn: 193992
2013-11-04 22:53:22 +08:00
// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
// shifted left by 1 bit.
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Fix issue with offset operand of BALC and BC instructions Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit. Differential Revision: http://reviews.llvm.org/D14770 llvm-svn: 254296
2015-11-30 20:56:18 +08:00
// DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
// shifted left by 1 bit.
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
Support for microMIPS jump instructions llvm-svn: 193623
2013-10-30 00:38:59 +08:00
// DecodeJumpTargetMM - Decode microMIPS jump target, which is
// shifted left by 1 bit.
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeMem(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips] Added support for various EVA ASE instructions. Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
2015-09-15 18:02:16 +08:00
static DecodeStatus DecodeMemEVA(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions Differential Revision: http://reviews.llvm.org/D11633 llvm-svn: 250511
2015-10-16 20:24:58 +08:00
static DecodeStatus DecodeLoadByte9(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeLoadByte15(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[Mips] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 309993
2017-08-04 06:12:30 +08:00
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder);
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
2014-10-01 16:26:55 +08:00
[mips] Added support for various EVA ASE instructions. Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
2015-09-15 18:02:16 +08:00
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. llvm-svn: 227430
2015-01-29 19:33:41 +08:00
[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions Differential Revision: http://reviews.llvm.org/D5204 llvm-svn: 224785
2014-12-24 03:55:34 +08:00
static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions Differential Revision: http://reviews.llvm.org/D11801 llvm-svn: 246999
2015-09-08 18:18:38 +08:00
static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement CACHEE and PREFE instructions Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125
2015-09-09 17:10:46 +08:00
static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips] Add synci instruction. Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
2014-11-28 01:28:10 +08:00
static DecodeStatus DecodeSyncI(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions Differential Revision: http://reviews.llvm.org/D12628 llvm-svn: 251510
2015-10-28 19:04:29 +08:00
static DecodeStatus DecodeSynciR6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement LWSP and SWSP instructions Differential Revision: http://reviews.llvm.org/D6416 llvm-svn: 224771
2014-12-24 00:16:33 +08:00
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement LWGP instruction Differential Revision: http://reviews.llvm.org/D6650 llvm-svn: 227325
2015-01-29 01:27:26 +08:00
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16 Differential Revision: http://reviews.llvm.org/D7436 llvm-svn: 228683
2015-02-10 20:41:13 +08:00
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement SW and SWE instructions Differential Revision: http://reviews.llvm.org/D10869 llvm-svn: 245293
2015-08-18 20:53:08 +08:00
static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
[Mips] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 309993
2017-08-04 06:12:30 +08:00
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder);
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
2014-10-01 16:26:55 +08:00
[Mips] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 309993
2017-08-04 06:12:30 +08:00
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder);
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
2014-10-01 16:26:55 +08:00
[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. llvm-svn: 226652
2015-01-21 18:47:36 +08:00
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
[Mips] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 309993
2017-08-04 06:12:30 +08:00
uint64_t Address, const void *Decoder);
[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. llvm-svn: 226652
2015-01-21 18:47:36 +08:00
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
2014-11-27 22:41:44 +08:00
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder);
[mips] Range check simm7. Summary: Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual encoding (it's a uimm7 except that 0x7f represents -1). Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18145 llvm-svn: 264056
2016-03-22 22:40:00 +08:00
static DecodeStatus DecodeLi16Imm(MCInst &Inst,
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
2014-11-27 22:41:44 +08:00
unsigned Value,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions Differential Revision: http://reviews.llvm.org/D11178 llvm-svn: 247146
2015-09-09 21:55:45 +08:00
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder);
[mips] Range check uimm6_lsl2. Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17291 llvm-svn: 263419
2016-03-14 19:16:56 +08:00
template <unsigned Bits, int Offset, int Scale>
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
uint64_t Address,
const void *Decoder);
[mips][ias] Range check uimm2 operands and fix a bug this revealed. Summary: The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA (unlike the MSA version) failed to account for the off-by-one encoding of the immediate. The range is actually 1..4 rather than 0..3. Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14015 llvm-svn: 252295
2015-11-06 20:22:31 +08:00
template <unsigned Bits, int Offset>
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
[mips] Range check uimm6_lsl2. Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17291 llvm-svn: 263419
2016-03-14 19:16:56 +08:00
uint64_t Address,
const void *Decoder) {
return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
Decoder);
}
[mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded. The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field. llvm-svn: 195004
2013-11-18 20:32:49 +08:00
[mips] Range check simm7. Summary: Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual encoding (it's a uimm7 except that 0x7f represents -1). Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18145 llvm-svn: 264056
2016-03-22 22:40:00 +08:00
template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
uint64_t Address,
const void *Decoder);
[mips] Range check simm4. Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16811 llvm-svn: 263220
2016-03-11 19:37:50 +08:00
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeInsSize(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][mips64r6] Add addiupc, aluipc, and auipc Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 llvm-svn: 208858
2014-05-15 18:45:58 +08:00
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
[mips][mips64r6] Add LDPC instruction Differential Revision: http://reviews.llvm.org/D3822 llvm-svn: 210460
2014-06-09 17:49:51 +08:00
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. llvm-svn: 223006
2014-12-01 19:12:04 +08:00
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
[mips][microMIPS] Implement ADDIUPC instruction Differential Revision: http://reviews.llvm.org/D6582 llvm-svn: 226656
2015-01-21 20:10:11 +08:00
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
/// handle.
template <typename InsnType>
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
2016-09-16 21:50:43 +08:00
template <typename InsnType>
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
template <typename InsnType>
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
2016-10-14 17:31:42 +08:00
template <typename InsnType>
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
template <typename InsnType>
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
template <typename InsnType>
static DecodeStatus
DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
template <typename InsnType>
static DecodeStatus
DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
template <typename InsnType>
static DecodeStatus
DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
template <typename InsnType>
static DecodeStatus
DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
template <typename InsnType>
static DecodeStatus
DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
template <typename InsnType>
static DecodeStatus
DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
template <typename InsnType>
static DecodeStatus
DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
template <typename InsnType>
static DecodeStatus
DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
template <typename InsnType>
static DecodeStatus
DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips][mips64r6] Add bgec and bgeuc instructions Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
2014-06-12 19:47:44 +08:00
template <typename InsnType>
static DecodeStatus
DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
template <typename InsnType>
static DecodeStatus
DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
template <typename InsnType>
static DecodeStatus
DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
[mips] Implement the 'dins' aliases. Traditionally GAS has provided automatic selection between dins, dinsm and dinsu. Binutils also disassembles all instructions in that family as 'dins' rather than the actual instruction. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34877 llvm-svn: 313267
2017-09-14 23:17:50 +08:00
template <typename InsnType>
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
const void *Decoder);
[mips] Implement the 'dext' aliases and it's disassembly alias. The other members of the dext family of instructions (dextm, dextu) are traditionally handled by the assembler selecting the right variant of 'dext' depending on the values of the position and size operands. When these instructions are disassembled, rather than reporting the actual instruction, an equivalent aliased form of 'dext' is generated and is reported. This is to mimic the behaviour of binutils. Reviewers: slthakur, nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D34887 llvm-svn: 313276
2017-09-15 01:27:53 +08:00
template <typename InsnType>
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
const void *Decoder);
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement SWM16 and LWM16 instructions Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
2014-11-28 02:28:59 +08:00
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
namespace llvm {
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
Move the global variables representing each Target behind accessor function This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
2016-10-10 07:00:34 +08:00
Target &getTheMipselTarget();
Target &getTheMipsTarget();
Target &getTheMips64Target();
Target &getTheMips64elTarget();
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
} // end namespace llvm
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static MCDisassembler *createMipsDisassembler(
const Target &T,
[MC] Require an MCContext when constructing an MCDisassembler. This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
2014-04-15 12:40:56 +08:00
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new MipsDisassembler(STI, Ctx, true);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
static MCDisassembler *createMipselDisassembler(
const Target &T,
[MC] Require an MCContext when constructing an MCDisassembler. This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
2014-04-15 12:40:56 +08:00
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new MipsDisassembler(STI, Ctx, false);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
extern "C" void LLVMInitializeMipsDisassembler() {
// Register the disassembler.
Move the global variables representing each Target behind accessor function This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
2016-10-10 07:00:34 +08:00
TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(),
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
createMipsDisassembler);
Move the global variables representing each Target behind accessor function This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
2016-10-10 07:00:34 +08:00
TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(),
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
createMipselDisassembler);
Move the global variables representing each Target behind accessor function This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
2016-10-10 07:00:34 +08:00
TargetRegistry::RegisterMCDisassembler(getTheMips64Target(),
[mips] Merge disassemblers into a single implementation. Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
2015-02-11 19:28:56 +08:00
createMipsDisassembler);
Move the global variables representing each Target behind accessor function This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
2016-10-10 07:00:34 +08:00
TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(),
[mips] Merge disassemblers into a single implementation. Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
2015-02-11 19:28:56 +08:00
createMipselDisassembler);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
Revert: [mips] Rewrite MipsAsmParser and MipsOperand.' due to buildbot errors in lld tests. It's currently unable to parse 'sym + imm' without surrounding parenthesis. llvm-svn: 205237
2014-04-01 02:51:43 +08:00
#include "MipsGenDisassemblerTables.inc"
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205229
2014-04-01 01:43:46 +08:00
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
[mips] Merge disassemblers into a single implementation. Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
2015-02-11 19:28:56 +08:00
const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
return *(RegInfo->getRegClass(RC).begin() + RegNo);
}
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
template <typename InsnType>
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder) {
[Mips] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 309993
2017-08-04 06:12:30 +08:00
using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
// The size of the n field depends on the element size
// The register class also depends on this.
InsnType tmp = fieldFromInstruction(insn, 17, 5);
unsigned NSize = 0;
DecodeFN RegDecoder = nullptr;
if ((tmp & 0x18) == 0x00) { // INSVE_B
NSize = 4;
RegDecoder = DecodeMSA128BRegisterClass;
} else if ((tmp & 0x1c) == 0x10) { // INSVE_H
NSize = 3;
RegDecoder = DecodeMSA128HRegisterClass;
} else if ((tmp & 0x1e) == 0x18) { // INSVE_W
NSize = 2;
RegDecoder = DecodeMSA128WRegisterClass;
} else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
NSize = 1;
RegDecoder = DecodeMSA128DRegisterClass;
} else
llvm_unreachable("Invalid encoding");
assert(NSize != 0 && RegDecoder != nullptr);
// $wd
tmp = fieldFromInstruction(insn, 6, 5);
if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
// $wd_in
if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
// $n
tmp = fieldFromInstruction(insn, 16, NSize);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createImm(tmp));
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
// $ws
tmp = fieldFromInstruction(insn, 11, 5);
if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
// $n2
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createImm(0));
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
return MCDisassembler::Success;
}
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
2016-09-16 21:50:43 +08:00
template <typename InsnType>
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder) {
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
2016-10-14 17:31:42 +08:00
InsnType Rs = fieldFromInstruction(insn, 16, 5);
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
2016-09-16 21:50:43 +08:00
InsnType Imm = fieldFromInstruction(insn, 0, 16);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
2016-10-14 17:31:42 +08:00
Rs)));
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
2016-09-16 21:50:43 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
2016-10-14 17:31:42 +08:00
Rs)));
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
2016-09-16 21:50:43 +08:00
MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
template <typename InsnType>
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder) {
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
2016-10-14 17:31:42 +08:00
InsnType Rs = fieldFromInstruction(insn, 21, 5);
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
2016-09-16 21:50:43 +08:00
InsnType Imm = fieldFromInstruction(insn, 0, 16);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
2016-10-14 17:31:42 +08:00
Rs)));
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
2016-09-16 21:50:43 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
2016-10-14 17:31:42 +08:00
Rs)));
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
2016-09-16 21:50:43 +08:00
MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
template <typename InsnType>
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the ADDI instruction from the earlier
// ISA's instead).
//
// We have:
// 0b001000 sssss ttttt iiiiiiiiiiiiiiii
// BOVC if rs >= rt
// BEQZALC if rs == 0 && rt != 0
// BEQC if rs < rt && rs != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5);
[MIPS][LLVM-MC] Fix Disassemble of Negative Offset Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
2016-05-24 17:57:10 +08:00
int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
bool HasRs = false;
if (Rs >= Rt) {
MI.setOpcode(Mips::BOVC);
HasRs = true;
} else if (Rs != 0 && Rs < Rt) {
MI.setOpcode(Mips::BEQC);
HasRs = true;
} else
MI.setOpcode(Mips::BEQZALC);
if (HasRs)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
Rs)));
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
Rt)));
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createImm(Imm));
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
template <typename InsnType>
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
InsnType Rt = fieldFromInstruction(insn, 21, 5);
InsnType Rs = fieldFromInstruction(insn, 16, 5);
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
int64_t Imm = 0;
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
if (Rs >= Rt) {
MI.setOpcode(Mips::BOVC_MMR6);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
} else if (Rs != 0 && Rs < Rt) {
MI.setOpcode(Mips::BEQC_MMR6);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
} else {
MI.setOpcode(Mips::BEQZALC_MMR6);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
}
MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
template <typename InsnType>
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the ADDI instruction from the earlier
// ISA's instead).
//
// We have:
// 0b011000 sssss ttttt iiiiiiiiiiiiiiii
// BNVC if rs >= rt
// BNEZALC if rs == 0 && rt != 0
// BNEC if rs < rt && rs != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5);
[MIPS][LLVM-MC] Fix Disassemble of Negative Offset Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
2016-05-24 17:57:10 +08:00
int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
bool HasRs = false;
if (Rs >= Rt) {
MI.setOpcode(Mips::BNVC);
HasRs = true;
} else if (Rs != 0 && Rs < Rt) {
MI.setOpcode(Mips::BNEC);
HasRs = true;
} else
MI.setOpcode(Mips::BNEZALC);
if (HasRs)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
Rs)));
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
Rt)));
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createImm(Imm));
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
template <typename InsnType>
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
InsnType Rt = fieldFromInstruction(insn, 21, 5);
InsnType Rs = fieldFromInstruction(insn, 16, 5);
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
int64_t Imm = 0;
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
if (Rs >= Rt) {
MI.setOpcode(Mips::BNVC_MMR6);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
} else if (Rs != 0 && Rs < Rt) {
MI.setOpcode(Mips::BNEC_MMR6);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
} else {
MI.setOpcode(Mips::BNEZALC_MMR6);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
}
MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
template <typename InsnType>
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
// We have:
// 0b110101 ttttt sssss iiiiiiiiiiiiiiii
// Invalid if rt == 0
// BGTZC_MMR6 if rs == 0 && rt != 0
// BLTZC_MMR6 if rs == rt && rt != 0
// BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
InsnType Rt = fieldFromInstruction(insn, 21, 5);
InsnType Rs = fieldFromInstruction(insn, 16, 5);
int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
bool HasRs = false;
if (Rt == 0)
return MCDisassembler::Fail;
else if (Rs == 0)
MI.setOpcode(Mips::BGTZC_MMR6);
else if (Rs == Rt)
MI.setOpcode(Mips::BLTZC_MMR6);
else {
MI.setOpcode(Mips::BLTC_MMR6);
HasRs = true;
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
}
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
if (HasRs)
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
template <typename InsnType>
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
// We have:
// 0b111101 ttttt sssss iiiiiiiiiiiiiiii
// Invalid if rt == 0
// BLEZC_MMR6 if rs == 0 && rt != 0
// BGEZC_MMR6 if rs == rt && rt != 0
// BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
InsnType Rt = fieldFromInstruction(insn, 21, 5);
InsnType Rs = fieldFromInstruction(insn, 16, 5);
int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
bool HasRs = false;
if (Rt == 0)
return MCDisassembler::Fail;
else if (Rs == 0)
MI.setOpcode(Mips::BLEZC_MMR6);
else if (Rs == Rt)
MI.setOpcode(Mips::BGEZC_MMR6);
else {
HasRs = true;
MI.setOpcode(Mips::BGEC_MMR6);
}
if (HasRs)
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
2016-06-09 20:57:23 +08:00
MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
template <typename InsnType>
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the BLEZL instruction from the earlier
// ISA's instead).
//
// We have:
// 0b010110 sssss ttttt iiiiiiiiiiiiiiii
// Invalid if rs == 0
// BLEZC if rs == 0 && rt != 0
// BGEZC if rs == rt && rt != 0
// BGEC if rs != rt && rs != 0 && rt != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5);
[MIPS][LLVM-MC] Fix Disassemble of Negative Offset Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
2016-05-24 17:57:10 +08:00
int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
[mips][mips64r6] Add bgec and bgeuc instructions Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
2014-06-12 19:47:44 +08:00
bool HasRs = false;
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
if (Rt == 0)
return MCDisassembler::Fail;
else if (Rs == 0)
MI.setOpcode(Mips::BLEZC);
else if (Rs == Rt)
MI.setOpcode(Mips::BGEZC);
[mips][mips64r6] Add bgec and bgeuc instructions Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
2014-06-12 19:47:44 +08:00
else {
HasRs = true;
MI.setOpcode(Mips::BGEC);
}
if (HasRs)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add bgec and bgeuc instructions Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
2014-06-12 19:47:44 +08:00
Rs)));
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
Rt)));
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createImm(Imm));
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
return MCDisassembler::Success;
}
template <typename InsnType>
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the BGTZL instruction from the earlier
// ISA's instead).
//
// We have:
// 0b010111 sssss ttttt iiiiiiiiiiiiiiii
// Invalid if rs == 0
// BGTZC if rs == 0 && rt != 0
// BLTZC if rs == rt && rt != 0
// BLTC if rs != rt && rs != 0 && rt != 0
[mips][mips64r6] Add BLTC and BLTUC instructions Differential Revision: http://reviews.llvm.org/D3923 llvm-svn: 211167
2014-06-18 22:36:00 +08:00
bool HasRs = false;
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5);
[MIPS][LLVM-MC] Fix Disassemble of Negative Offset Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
2016-05-24 17:57:10 +08:00
int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
if (Rt == 0)
return MCDisassembler::Fail;
else if (Rs == 0)
MI.setOpcode(Mips::BGTZC);
else if (Rs == Rt)
MI.setOpcode(Mips::BLTZC);
[mips][mips64r6] Add BLTC and BLTUC instructions Differential Revision: http://reviews.llvm.org/D3923 llvm-svn: 211167
2014-06-18 22:36:00 +08:00
else {
MI.setOpcode(Mips::BLTC);
HasRs = true;
}
if (HasRs)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add BLTC and BLTUC instructions Differential Revision: http://reviews.llvm.org/D3923 llvm-svn: 211167
2014-06-18 22:36:00 +08:00
Rs)));
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
Rt)));
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createImm(Imm));
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
return MCDisassembler::Success;
}
template <typename InsnType>
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the BGTZ instruction from the earlier
// ISA's instead).
//
// We have:
// 0b000111 sssss ttttt iiiiiiiiiiiiiiii
// BGTZ if rt == 0
// BGTZALC if rs == 0 && rt != 0
// BLTZALC if rs != 0 && rs == rt
// BLTUC if rs != 0 && rs != rt
InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5);
[MIPS][LLVM-MC] Fix Disassemble of Negative Offset Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
2016-05-24 17:57:10 +08:00
int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
bool HasRs = false;
bool HasRt = false;
if (Rt == 0) {
MI.setOpcode(Mips::BGTZ);
HasRs = true;
} else if (Rs == 0) {
MI.setOpcode(Mips::BGTZALC);
HasRt = true;
} else if (Rs == Rt) {
MI.setOpcode(Mips::BLTZALC);
HasRs = true;
[mips][mips64r6] Add BLTC and BLTUC instructions Differential Revision: http://reviews.llvm.org/D3923 llvm-svn: 211167
2014-06-18 22:36:00 +08:00
} else {
MI.setOpcode(Mips::BLTUC);
HasRs = true;
HasRt = true;
}
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
if (HasRs)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
Rs)));
if (HasRt)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
Rt)));
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createImm(Imm));
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
[mips][mips64r6] Add bgec and bgeuc instructions Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
2014-06-12 19:47:44 +08:00
return MCDisassembler::Success;
}
template <typename InsnType>
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the BLEZL instruction from the earlier
// ISA's instead).
//
// We have:
// 0b000110 sssss ttttt iiiiiiiiiiiiiiii
// Invalid if rs == 0
// BLEZALC if rs == 0 && rt != 0
// BGEZALC if rs == rt && rt != 0
// BGEUC if rs != rt && rs != 0 && rt != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5);
[MIPS][LLVM-MC] Fix Disassemble of Negative Offset Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
2016-05-24 17:57:10 +08:00
int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
[mips][mips64r6] Add bgec and bgeuc instructions Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
2014-06-12 19:47:44 +08:00
bool HasRs = false;
if (Rt == 0)
return MCDisassembler::Fail;
else if (Rs == 0)
MI.setOpcode(Mips::BLEZALC);
else if (Rs == Rt)
MI.setOpcode(Mips::BGEZALC);
else {
HasRs = true;
MI.setOpcode(Mips::BGEUC);
}
if (HasRs)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add bgec and bgeuc instructions Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
2014-06-12 19:47:44 +08:00
Rs)));
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
[mips][mips64r6] Add bgec and bgeuc instructions Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
2014-06-12 19:47:44 +08:00
Rt)));
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
MI.addOperand(MCOperand::createImm(Imm));
[mips][mips64r6] Add bgec and bgeuc instructions Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
2014-06-12 19:47:44 +08:00
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
return MCDisassembler::Success;
}
[mips] Implement the 'dext' aliases and it's disassembly alias. The other members of the dext family of instructions (dextm, dextu) are traditionally handled by the assembler selecting the right variant of 'dext' depending on the values of the position and size operands. When these instructions are disassembled, rather than reporting the actual instruction, an equivalent aliased form of 'dext' is generated and is reported. This is to mimic the behaviour of binutils. Reviewers: slthakur, nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D34887 llvm-svn: 313276
2017-09-15 01:27:53 +08:00
// Override the generated disassembler to produce DEXT all the time. This is
// for feature / behaviour parity with binutils.
template <typename InsnType>
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
const void *Decoder) {
unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
unsigned Size = 0;
unsigned Pos = 0;
bool IsMicroMips = false;
switch (MI.getOpcode()) {
case Mips::DEXT_MM64R6:
IsMicroMips = true;
LLVM_FALLTHROUGH;
case Mips::DEXT:
Pos = Lsb;
Size = Msbd + 1;
break;
case Mips::DEXTM_MM64R6:
IsMicroMips = true;
LLVM_FALLTHROUGH;
case Mips::DEXTM:
Pos = Lsb;
Size = Msbd + 1 + 32;
break;
case Mips::DEXTU_MM64R6:
IsMicroMips = true;
LLVM_FALLTHROUGH;
case Mips::DEXTU:
Pos = Lsb + 32;
Size = Msbd + 1;
break;
default:
llvm_unreachable("Unknown DEXT instruction!");
}
MI.setOpcode(IsMicroMips ? Mips::DEXT_MM64R6 : Mips::DEXT);
// Although the format of the instruction is similar, rs and rt are swapped
// for microMIPS64R6.
InsnType Rs = fieldFromInstruction(Insn, 21, 5);
InsnType Rt = fieldFromInstruction(Insn, 16, 5);
if (IsMicroMips)
std::swap(Rs, Rt);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
MI.addOperand(MCOperand::createImm(Pos));
MI.addOperand(MCOperand::createImm(Size));
return MCDisassembler::Success;
}
[mips] Implement the 'dins' aliases. Traditionally GAS has provided automatic selection between dins, dinsm and dinsu. Binutils also disassembles all instructions in that family as 'dins' rather than the actual instruction. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34877 llvm-svn: 313267
2017-09-14 23:17:50 +08:00
// Override the generated disassembler to produce DINS all the time. This is
// for feature / behaviour parity with binutils.
template <typename InsnType>
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
const void *Decoder) {
unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
unsigned Size = 0;
unsigned Pos = 0;
bool IsMicroMips = false;
switch (MI.getOpcode()) {
case Mips::DINS_MM64R6:
IsMicroMips = true;
LLVM_FALLTHROUGH;
case Mips::DINS:
Pos = Lsb;
Size = Msbd + 1 - Pos;
break;
case Mips::DINSM_MM64R6:
IsMicroMips = true;
LLVM_FALLTHROUGH;
case Mips::DINSM:
Pos = Lsb;
Size = Msbd + 33 - Pos;
break;
case Mips::DINSU_MM64R6:
IsMicroMips = true;
LLVM_FALLTHROUGH;
case Mips::DINSU:
Pos = Lsb + 32;
// mbsd = pos + size - 33
// mbsd - pos + 33 = size
Size = Msbd + 33 - Pos;
break;
default:
llvm_unreachable("Unknown DINS instruction!");
}
// Although the format of the instruction is similar, rs and rt are swapped
// for microMIPS64R6.
InsnType Rs = fieldFromInstruction(Insn, 21, 5);
InsnType Rt = fieldFromInstruction(Insn, 16, 5);
if (IsMicroMips)
std::swap(Rs, Rt);
MI.setOpcode(IsMicroMips ? Mips::DINS_MM64R6 : Mips::DINS);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
MI.addOperand(MCOperand::createImm(Pos));
MI.addOperand(MCOperand::createImm(Size));
return MCDisassembler::Success;
}
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
Fix spelling mistakes in MIPS target comments. NFC. Identified by Pedro Giffuni in PR27636. llvm-svn: 287338
2016-11-18 19:53:36 +08:00
/// according to the given endianness.
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
uint64_t &Size, uint32_t &Insn,
bool IsBigEndian) {
// We want to read exactly 2 Bytes of data.
if (Bytes.size() < 2) {
Size = 0;
return MCDisassembler::Fail;
}
if (IsBigEndian) {
Insn = (Bytes[0] << 8) | Bytes[1];
} else {
Insn = (Bytes[1] << 8) | Bytes[0];
}
return MCDisassembler::Success;
}
Pass an ArrayRef to MCDisassembler::getInstruction. With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
2014-11-12 10:04:27 +08:00
/// Read four bytes from the ArrayRef and return 32 bit word sorted
Fix spelling mistakes in MIPS target comments. NFC. Identified by Pedro Giffuni in PR27636. llvm-svn: 287338
2016-11-18 19:53:36 +08:00
/// according to the given endianness.
Pass an ArrayRef to MCDisassembler::getInstruction. With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
2014-11-12 10:04:27 +08:00
static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
uint64_t &Size, uint32_t &Insn,
bool IsBigEndian, bool IsMicroMips) {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
// We want to read exactly 4 Bytes of data.
Pass an ArrayRef to MCDisassembler::getInstruction. With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
2014-11-12 10:04:27 +08:00
if (Bytes.size() < 4) {
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
Size = 0;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Fail;
}
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
// High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
// always precede the low 16 bits in the instruction stream (that is, they
// are placed at lower addresses in the instruction stream).
//
// microMIPS byte ordering:
// Big-endian: 0 | 1 | 2 | 3
// Little-endian: 1 | 0 | 3 | 2
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
if (IsBigEndian) {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
// Encoded as a big-endian 32-bit word in the stream.
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
Insn =
(Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
} else {
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
if (IsMicroMips) {
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
(Bytes[1] << 24);
} else {
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
(Bytes[3] << 24);
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
return MCDisassembler::Success;
}
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
Pass an ArrayRef to MCDisassembler::getInstruction. With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
2014-11-12 10:04:27 +08:00
ArrayRef<uint8_t> Bytes,
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
uint64_t Address,
raw_ostream &VStream,
raw_ostream &CStream) const {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
uint32_t Insn;
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
DecodeStatus Result;
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
Size = 0;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
if (IsMicroMips) {
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
Fix UMRs in Mips disassembler on invalid instruction streams The Insn and Size local variables were used without initialization. llvm-svn: 253607
2015-11-20 05:51:55 +08:00
if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail;
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
[mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions Differential Revision: http://reviews.llvm.org/D11181 llvm-svn: 246963
2015-09-07 19:56:37 +08:00
if (hasMips32r6()) {
DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
// Calling the auto-generated decoder function for microMIPS32R6
// (and microMIPS64R6) 16-bit instructions.
Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
Address, this, STI);
if (Result != MCDisassembler::Fail) {
Size = 2;
return Result;
}
}
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
[mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions Differential Revision: http://reviews.llvm.org/D11181 llvm-svn: 246963
2015-09-07 19:56:37 +08:00
// Calling the auto-generated decoder function for microMIPS 16-bit
// instructions.
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
this, STI);
if (Result != MCDisassembler::Fail) {
Size = 2;
return Result;
}
Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail;
[mips][microMIPSr6] Implement disassembler support Implement disassembler support for microMIPS32r6. Differential Revision: http://reviews.llvm.org/D8490 llvm-svn: 235307
2015-04-20 22:40:38 +08:00
if (hasMips32r6()) {
DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
// Calling the auto-generated decoder function.
[mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions Differential Revision: http://reviews.llvm.org/D10923 llvm-svn: 244744
2015-08-12 20:45:16 +08:00
Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
[mips][microMIPSr6] Implement disassembler support Implement disassembler support for microMIPS32r6. Differential Revision: http://reviews.llvm.org/D8490 llvm-svn: 235307
2015-04-20 22:40:38 +08:00
this, STI);
[mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions Differential Revision: http://reviews.llvm.org/D11181 llvm-svn: 246963
2015-09-07 19:56:37 +08:00
if (Result != MCDisassembler::Fail) {
Size = 4;
return Result;
}
[mips][microMIPSr6] Implement disassembler support Implement disassembler support for microMIPS32r6. Differential Revision: http://reviews.llvm.org/D8490 llvm-svn: 235307
2015-04-20 22:40:38 +08:00
}
[mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions Differential Revision: http://reviews.llvm.org/D10923 llvm-svn: 244744
2015-08-12 20:45:16 +08:00
[mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions Differential Revision: http://reviews.llvm.org/D11181 llvm-svn: 246963
2015-09-07 19:56:37 +08:00
DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
// Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
this, STI);
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
if (Result != MCDisassembler::Fail) {
Size = 4;
return Result;
}
[mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions Differential Revision: http://reviews.llvm.org/D17328 llvm-svn: 264246
2016-03-24 16:02:09 +08:00
[mips] Place certain 64 bit FPU instructions in their own decoder namespace Previously, instructions that were defined to use the FGR64 register class were associated with the Mips64 table which was incorrect. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38454 llvm-svn: 314976
2017-10-05 18:27:37 +08:00
if (isFP64()) {
DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
[mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions Differential Revision: http://reviews.llvm.org/D17328 llvm-svn: 264246
2016-03-24 16:02:09 +08:00
Address, this, STI);
if (Result != MCDisassembler::Fail) {
Size = 4;
return Result;
}
}
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
// This is an invalid instruction. Claim that the Size is 2 bytes. Since
// microMIPS instructions have a minimum alignment of 2, the next 2 bytes
// could form a valid instruction. The two bytes we rejected as an
// instruction could have actually beeen an inline constant pool that is
// unconditionally branched over.
Fix UMRs in Mips disassembler on invalid instruction streams The Insn and Size local variables were used without initialization. llvm-svn: 253607
2015-11-20 05:51:55 +08:00
Size = 2;
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
return MCDisassembler::Fail;
}
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
// Attempt to read the instruction so that we can attempt to decode it. If
// the buffer is not 4 bytes long, let the higher level logic figure out
// what to do with a size of zero and MCDisassembler::Fail.
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
if (Result == MCDisassembler::Fail)
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
return MCDisassembler::Fail;
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
// The only instruction size for standard encoded MIPS.
Size = 4;
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
[mips] Add cache and pref instructions Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
2014-06-13 21:15:59 +08:00
if (hasCOP3()) {
DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
Result =
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
if (Result != MCDisassembler::Fail)
[mips] Add cache and pref instructions Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
2014-06-13 21:15:59 +08:00
return Result;
}
if (hasMips32r6() && isGP64()) {
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
Address, this, STI);
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
if (Result != MCDisassembler::Fail)
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
return Result;
}
[mips][atomics] Fix atomic instruction descriptions and uses. PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
2016-06-14 19:29:28 +08:00
if (hasMips32r6() && isPTR64()) {
DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
Address, this, STI);
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
if (Result != MCDisassembler::Fail)
[mips][atomics] Fix atomic instruction descriptions and uses. PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
2016-06-14 19:29:28 +08:00
return Result;
}
[mips] Add cache and pref instructions Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
2014-06-13 21:15:59 +08:00
if (hasMips32r6()) {
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
Address, this, STI);
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
if (Result != MCDisassembler::Fail)
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
return Result;
}
[mips][atomics] Fix atomic instruction descriptions and uses. PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
2016-06-14 19:29:28 +08:00
if (hasMips2() && isPTR64()) {
DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
Address, this, STI);
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
if (Result != MCDisassembler::Fail)
[mips][atomics] Fix atomic instruction descriptions and uses. PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
2016-06-14 19:29:28 +08:00
return Result;
}
[mips] Add new format for dmtc2/dmfc2 for Octeon CPUs. Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1. I had to introduce a new deconding namespace to avoid a decoding conflict. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D10083 llvm-svn: 238439
2015-05-29 00:23:16 +08:00
if (hasCnMips()) {
DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
Address, this, STI);
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
if (Result != MCDisassembler::Fail)
[mips] Add new format for dmtc2/dmfc2 for Octeon CPUs. Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1. I had to introduce a new deconding namespace to avoid a decoding conflict. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D10083 llvm-svn: 238439
2015-05-29 00:23:16 +08:00
return Result;
}
[mips] Merge disassemblers into a single implementation. Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
2015-02-11 19:28:56 +08:00
if (isGP64()) {
DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
Address, this, STI);
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
if (Result != MCDisassembler::Fail)
[mips] Merge disassemblers into a single implementation. Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
2015-02-11 19:28:56 +08:00
return Result;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
[mips] Place certain 64 bit FPU instructions in their own decoder namespace Previously, instructions that were defined to use the FGR64 register class were associated with the Mips64 table which was incorrect. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38454 llvm-svn: 314976
2017-10-05 18:27:37 +08:00
if (isFP64()) {
DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn,
Address, this, STI);
if (Result != MCDisassembler::Fail)
return Result;
}
[mips] Merge disassemblers into a single implementation. Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
2015-02-11 19:28:56 +08:00
DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
// Calling the auto-generated decoder function.
Misc style fixes. NFC. This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
2014-11-11 02:11:10 +08:00
Result =
decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
[mips][mc] Fix a crash when disassembling odd sized sections Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
2017-02-24 18:50:27 +08:00
if (Result != MCDisassembler::Fail)
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return Result;
return MCDisassembler::Fail;
}
Remove the form field from Mips16 instruction formats and set things up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. llvm-svn: 175126
2013-02-14 11:05:25 +08:00
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
return MCDisassembler::Fail;
}
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
if (RegNo > 31)
return MCDisassembler::Fail;
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement microMIPS 16-bit instructions registers Differential Revision: http://reviews.llvm.org/D5116 llvm-svn: 220273
2014-10-21 16:23:11 +08:00
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][microMIPS] Implement disassembler support for 16-bit instructions With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
2014-11-24 21:29:59 +08:00
return MCDisassembler::Success;
[mips][microMIPS] Implement microMIPS 16-bit instructions registers Differential Revision: http://reviews.llvm.org/D5116 llvm-svn: 220273
2014-10-21 16:23:11 +08:00
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
[mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0 Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17. Differential Revision: http://reviews.llvm.org/D5780 llvm-svn: 222652
2014-11-24 22:25:53 +08:00
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
return MCDisassembler::Success;
[mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0 Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17. Differential Revision: http://reviews.llvm.org/D5780 llvm-svn: 222652
2014-11-24 22:25:53 +08:00
}
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
return MCDisassembler::Success;
}
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
if (RegNo > 31)
return MCDisassembler::Fail;
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions. Also, fix predicates. llvm-svn: 189432
2013-08-28 08:55:15 +08:00
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[mips] Merge disassemblers into a single implementation. Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
2015-02-11 19:28:56 +08:00
if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions. Also, fix predicates. llvm-svn: 189432
2013-08-28 08:55:15 +08:00
return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
}
[mips] Rename DSPRegs. llvm-svn: 188342
2013-08-14 08:53:38 +08:00
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
MIPS DSP: add functions which decode DSP and accumulator registers. llvm-svn: 164748
2012-09-27 10:01:10 +08:00
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg function to lookup the proper tablegen'ed register enumeration. Previously, it was using the encoded value directly. llvm-svn: 185026
2013-06-27 06:23:32 +08:00
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips] Fix FP branch instructions to have explicit FP condition code register operands. llvm-svn: 187238
2013-07-27 04:13:47 +08:00
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips] Fix FP branch instructions to have explicit FP condition code register operands. llvm-svn: 187238
2013-07-27 04:13:47 +08:00
return MCDisassembler::Success;
}
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
if (RegNo > 31)
return MCDisassembler::Fail;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeMem(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
[mips] Added support for various EVA ASE instructions. Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
2015-09-15 18:02:16 +08:00
if (Inst.getOpcode() == Mips::SC ||
Inst.getOpcode() == Mips::SCD)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips] Added support for various EVA ASE instructions. Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
2015-09-15 18:02:16 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeMemEVA(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<9>(Insn >> 7);
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
if (Inst.getOpcode() == Mips::SCE)
Inst.addOperand(MCOperand::createReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
[mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions Differential Revision: http://reviews.llvm.org/D11633 llvm-svn: 250511
2015-10-16 20:24:58 +08:00
return MCDisassembler::Success;
}
static DecodeStatus DecodeLoadByte9(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<9>(Insn & 0x1ff);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeLoadByte15(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
2014-10-01 16:26:55 +08:00
static DecodeStatus DecodeCacheOp(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
unsigned Hint = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
Inst.addOperand(MCOperand::createImm(Hint));
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
2014-10-01 16:26:55 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions Differential Revision: http://reviews.llvm.org/D5204 llvm-svn: 224785
2014-12-24 03:55:34 +08:00
static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<12>(Insn & 0xfff);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
unsigned Hint = fieldFromInstruction(Insn, 21, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
Inst.addOperand(MCOperand::createImm(Hint));
[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions Differential Revision: http://reviews.llvm.org/D5204 llvm-svn: 224785
2014-12-24 03:55:34 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement CACHEE and PREFE instructions Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125
2015-09-09 17:10:46 +08:00
static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<9>(Insn & 0x1ff);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
unsigned Hint = fieldFromInstruction(Insn, 21, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
Inst.addOperand(MCOperand::createImm(Hint));
return MCDisassembler::Success;
}
[mips] Added support for various EVA ASE instructions. Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
2015-09-15 18:02:16 +08:00
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<9>(Insn >> 7);
[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. llvm-svn: 227430
2015-01-29 19:33:41 +08:00
unsigned Hint = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
Inst.addOperand(MCOperand::createImm(Hint));
[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. llvm-svn: 227430
2015-01-29 19:33:41 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions Differential Revision: http://reviews.llvm.org/D11801 llvm-svn: 246999
2015-09-08 18:18:38 +08:00
static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<9>(Insn & 0x1ff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
[mips] Add synci instruction. Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
2014-11-28 01:28:10 +08:00
static DecodeStatus DecodeSyncI(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
[mips] Add synci instruction. Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
2014-11-28 01:28:10 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions Differential Revision: http://reviews.llvm.org/D12628 llvm-svn: 251510
2015-10-28 19:04:29 +08:00
static DecodeStatus DecodeSynciR6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Immediate = SignExtend32<16>(Insn & 0xffff);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Immediate));
return MCDisassembler::Success;
}
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
unsigned Reg = fieldFromInstruction(Insn, 6, 5);
unsigned Base = fieldFromInstruction(Insn, 11, 5);
Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
[mips][msa] Fix issue with immediate fields of LD/ST instructions not being correctly encoded/decoded. In more detail, immediate fields of LD/ST instructions should be divided/multiplied by the size of the data format before encoding and after decoding, respectively. llvm-svn: 196494
2013-12-05 19:06:22 +08:00
// The immediate field of an LD/ST instruction is scaled which means it must
// be multiplied (when decoding) by the size (in bytes) of the instructions'
// data format.
// .b - 1 byte
// .h - 2 bytes
// .w - 4 bytes
// .d - 8 bytes
switch(Inst.getOpcode())
{
default:
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 293729
2017-02-01 09:22:51 +08:00
assert(false && "Unexpected instruction");
[mips][msa] Fix issue with immediate fields of LD/ST instructions not being correctly encoded/decoded. In more detail, immediate fields of LD/ST instructions should be divided/multiplied by the size of the data format before encoding and after decoding, respectively. llvm-svn: 196494
2013-12-05 19:06:22 +08:00
return MCDisassembler::Fail;
break;
case Mips::LD_B:
case Mips::ST_B:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(Offset));
[mips][msa] Fix issue with immediate fields of LD/ST instructions not being correctly encoded/decoded. In more detail, immediate fields of LD/ST instructions should be divided/multiplied by the size of the data format before encoding and after decoding, respectively. llvm-svn: 196494
2013-12-05 19:06:22 +08:00
break;
case Mips::LD_H:
case Mips::ST_H:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(Offset * 2));
[mips][msa] Fix issue with immediate fields of LD/ST instructions not being correctly encoded/decoded. In more detail, immediate fields of LD/ST instructions should be divided/multiplied by the size of the data format before encoding and after decoding, respectively. llvm-svn: 196494
2013-12-05 19:06:22 +08:00
break;
case Mips::LD_W:
case Mips::ST_W:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(Offset * 4));
[mips][msa] Fix issue with immediate fields of LD/ST instructions not being correctly encoded/decoded. In more detail, immediate fields of LD/ST instructions should be divided/multiplied by the size of the data format before encoding and after decoding, respectively. llvm-svn: 196494
2013-12-05 19:06:22 +08:00
break;
case Mips::LD_D:
case Mips::ST_D:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(Offset * 8));
[mips][msa] Fix issue with immediate fields of LD/ST instructions not being correctly encoded/decoded. In more detail, immediate fields of LD/ST instructions should be divided/multiplied by the size of the data format before encoding and after decoding, respectively. llvm-svn: 196494
2013-12-05 19:06:22 +08:00
break;
}
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned Offset = Insn & 0xf;
unsigned Reg = fieldFromInstruction(Insn, 7, 3);
unsigned Base = fieldFromInstruction(Insn, 4, 3);
switch (Inst.getOpcode()) {
case Mips::LBU16_MM:
case Mips::LHU16_MM:
case Mips::LW16_MM:
if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
== MCDisassembler::Fail)
return MCDisassembler::Fail;
break;
case Mips::SB16_MM:
[mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
2015-11-12 21:21:33 +08:00
case Mips::SB16_MMR6:
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
case Mips::SH16_MM:
[mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
2015-11-12 21:21:33 +08:00
case Mips::SH16_MMR6:
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
case Mips::SW16_MM:
[mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
2015-11-12 21:21:33 +08:00
case Mips::SW16_MMR6:
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
== MCDisassembler::Fail)
return MCDisassembler::Fail;
break;
}
if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
== MCDisassembler::Fail)
return MCDisassembler::Fail;
switch (Inst.getOpcode()) {
case Mips::LBU16_MM:
if (Offset == 0xf)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(-1));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
else
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(Offset));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
break;
case Mips::SB16_MM:
[mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
2015-11-12 21:21:33 +08:00
case Mips::SB16_MMR6:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(Offset));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
break;
case Mips::LHU16_MM:
case Mips::SH16_MM:
[mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
2015-11-12 21:21:33 +08:00
case Mips::SH16_MMR6:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(Offset << 1));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
break;
case Mips::LW16_MM:
case Mips::SW16_MM:
[mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
2015-11-12 21:21:33 +08:00
case Mips::SW16_MMR6:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(Offset << 2));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
2014-11-27 02:56:38 +08:00
break;
}
return MCDisassembler::Success;
}
[mips][microMIPS] Implement LWSP and SWSP instructions Differential Revision: http://reviews.llvm.org/D6416 llvm-svn: 224771
2014-12-24 00:16:33 +08:00
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned Offset = Insn & 0x1F;
unsigned Reg = fieldFromInstruction(Insn, 5, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Mips::SP));
Inst.addOperand(MCOperand::createImm(Offset << 2));
[mips][microMIPS] Implement LWSP and SWSP instructions Differential Revision: http://reviews.llvm.org/D6416 llvm-svn: 224771
2014-12-24 00:16:33 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement LWGP instruction Differential Revision: http://reviews.llvm.org/D6650 llvm-svn: 227325
2015-01-29 01:27:26 +08:00
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned Offset = Insn & 0x7F;
unsigned Reg = fieldFromInstruction(Insn, 7, 3);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Mips::GP));
Inst.addOperand(MCOperand::createImm(Offset << 2));
[mips][microMIPS] Implement LWGP instruction Differential Revision: http://reviews.llvm.org/D6650 llvm-svn: 227325
2015-01-29 01:27:26 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16 Differential Revision: http://reviews.llvm.org/D7436 llvm-svn: 228683
2015-02-10 20:41:13 +08:00
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
[mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
2015-11-12 21:21:33 +08:00
int Offset;
switch (Inst.getOpcode()) {
case Mips::LWM16_MMR6:
case Mips::SWM16_MMR6:
Offset = fieldFromInstruction(Insn, 4, 4);
break;
default:
Offset = SignExtend32<4>(Insn & 0xf);
break;
}
[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16 Differential Revision: http://reviews.llvm.org/D7436 llvm-svn: 228683
2015-02-10 20:41:13 +08:00
if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
== MCDisassembler::Fail)
return MCDisassembler::Fail;
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::SP));
Inst.addOperand(MCOperand::createImm(Offset << 2));
[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16 Differential Revision: http://reviews.llvm.org/D7436 llvm-svn: 228683
2015-02-10 20:41:13 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement SW and SWE instructions Differential Revision: http://reviews.llvm.org/D10869 llvm-svn: 245293
2015-08-18 20:53:08 +08:00
static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<9>(Insn & 0x1ff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
[mips][microMIPS] Implement LLE and SCE instructions Differential Revision: http://reviews.llvm.org/D11630 llvm-svn: 250379
2015-10-15 16:11:50 +08:00
if (Inst.getOpcode() == Mips::SCE_MM)
Inst.addOperand(MCOperand::createReg(Reg));
[mips][microMIPS] Implement SW and SWE instructions Differential Revision: http://reviews.llvm.org/D10869 llvm-svn: 245293
2015-08-18 20:53:08 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<12>(Insn & 0x0fff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
switch (Inst.getOpcode()) {
case Mips::SWM32_MM:
case Mips::LWM32_MM:
if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
== MCDisassembler::Fail)
return MCDisassembler::Fail;
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
break;
case Mips::SC_MM:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Replace "fallthrough" comments with LLVM_FALLTHROUGH This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
2016-08-17 13:10:15 +08:00
LLVM_FALLTHROUGH;
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
default:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][microMIPS] Implement LWP and SWP instructions Differential Revision: http://reviews.llvm.org/D10640 llvm-svn: 268896
2016-05-09 16:07:28 +08:00
if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM ||
Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg+1));
[mips][microMIPS] Implement SWP and LWP instructions Differential Revision: http://reviews.llvm.org/D5667 llvm-svn: 224338
2014-12-16 22:59:10 +08:00
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
}
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
return MCDisassembler::Success;
}
static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeFMem(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
2014-10-01 16:26:55 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
// This function is the same as DecodeFMem but with the Reg and Base fields
// swapped according to microMIPS spec.
int Offset = SignExtend32<16>(Insn & 0xffff);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
2014-10-01 16:26:55 +08:00
static DecodeStatus DecodeFMem2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
2014-10-01 16:26:55 +08:00
return MCDisassembler::Success;
}
static DecodeStatus DecodeFMem3(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. llvm-svn: 226652
2015-01-21 18:47:36 +08:00
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<11>(Insn & 0x07ff);
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 11, 5);
Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. llvm-svn: 226652
2015-01-21 18:47:36 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
int Offset = SignExtend32<11>(Insn & 0x07ff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
unsigned Rt = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Rt));
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
}
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Rt));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
// Currently only hardware register 29 is supported.
if (RegNo != 29)
return MCDisassembler::Fail;
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::HWR29));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
if (RegNo > 30 || RegNo %2)
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Fail;
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
MIPS DSP: add functions which decode DSP and accumulator registers. llvm-svn: 164748
2012-09-27 10:01:10 +08:00
if (RegNo >= 4)
return MCDisassembler::Fail;
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
MIPS DSP: add functions which decode DSP and accumulator registers. llvm-svn: 164748
2012-09-27 10:01:10 +08:00
return MCDisassembler::Success;
}
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
if (RegNo >= 4)
return MCDisassembler::Fail;
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
return MCDisassembler::Success;
}
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
if (RegNo >= 4)
return MCDisassembler::Fail;
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
return MCDisassembler::Success;
}
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
return MCDisassembler::Success;
}
[mips][msa] Direct Object Emission support for the MSA instruction set. In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
2013-09-26 07:50:44 +08:00
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][msa] Direct Object Emission support for the MSA instruction set. In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
2013-09-26 07:50:44 +08:00
return MCDisassembler::Success;
}
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][msa] Direct Object Emission support for the MSA instruction set. In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
2013-09-26 07:50:44 +08:00
return MCDisassembler::Success;
}
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][msa] Direct Object Emission support for the MSA instruction set. In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
2013-09-26 07:50:44 +08:00
return MCDisassembler::Success;
}
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
2013-10-21 20:26:50 +08:00
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
2013-10-21 20:26:50 +08:00
return MCDisassembler::Success;
[mips][mips64r6] Add bc[12](eq|ne)z Summary: Depends on D3691 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3760 llvm-svn: 209292
2014-05-21 20:56:39 +08:00
}
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
[mips][mips64r6] Add bc[12](eq|ne)z Summary: Depends on D3691 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3760 llvm-svn: 209292
2014-05-21 20:56:39 +08:00
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Reg));
[mips][mips64r6] Add bc[12](eq|ne)z Summary: Depends on D3691 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3760 llvm-svn: 209292
2014-05-21 20:56:39 +08:00
return MCDisassembler::Success;
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
2013-10-21 20:26:50 +08:00
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeBranchTarget(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
Fix left shifts of negative values in MipsDisassembler. This bug was reported by UBSan. llvm-svn: 216920
2014-09-03 01:49:16 +08:00
int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(BranchOffset));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and MULSAQ_S.W.PH instructions Differential Revision: http://reviews.llvm.org/D14117 llvm-svn: 269408
2016-05-13 19:32:53 +08:00
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(JumpOffset));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
[MIPS][LLVM-MC] Fix Disassemble of Negative Offset Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
2016-05-24 17:57:10 +08:00
int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(BranchOffset));
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement BEQZC and BNEZC instructions Differential Revision: http://reviews.llvm.org/D15417 llvm-svn: 269755
2016-05-17 19:10:15 +08:00
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
[mips][microMIPS] Implement BEQZC and BNEZC instructions Differential Revision: http://reviews.llvm.org/D15417 llvm-svn: 269755
2016-05-17 19:10:15 +08:00
Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
[MIPS][LLVM-MC] Fix Disassemble of Negative Offset Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
2016-05-24 17:57:10 +08:00
int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(BranchOffset));
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions Differential Revision: http://reviews.llvm.org/D5271 llvm-svn: 225627
2015-01-12 20:03:34 +08:00
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
[mips] Fix calculation of a branch instruction offset to escape left shift of negative value llvm-svn: 313815
2017-09-21 05:01:30 +08:00
int32_t BranchOffset = SignExtend32<8>(Offset << 1);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(BranchOffset));
[mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions Differential Revision: http://reviews.llvm.org/D5271 llvm-svn: 225627
2015-01-12 20:03:34 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226657
2015-01-21 20:39:30 +08:00
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
[mips] Fix calculation of a branch instruction offset to escape left shift of negative value llvm-svn: 313815
2017-09-21 05:01:30 +08:00
int32_t BranchOffset = SignExtend32<11>(Offset << 1);
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(BranchOffset));
[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226657
2015-01-21 20:39:30 +08:00
return MCDisassembler::Success;
}
Support for microMIPS branch instructions. llvm-svn: 193992
2013-11-04 22:53:22 +08:00
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(BranchOffset));
Support for microMIPS branch instructions. llvm-svn: 193992
2013-11-04 22:53:22 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Fix issue with offset operand of BALC and BC instructions Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit. Differential Revision: http://reviews.llvm.org/D14770 llvm-svn: 254296
2015-11-30 20:56:18 +08:00
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
[mips] Fix calculation of a branch instruction offset to escape left shift of negative value llvm-svn: 313815
2017-09-21 05:01:30 +08:00
int32_t BranchOffset = SignExtend32<27>(Offset << 1);
[mips][microMIPS] Fix issue with offset operand of BALC and BC instructions Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit. Differential Revision: http://reviews.llvm.org/D14770 llvm-svn: 254296
2015-11-30 20:56:18 +08:00
Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
Support for microMIPS jump instructions llvm-svn: 193623
2013-10-30 00:38:59 +08:00
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(JumpOffset));
Support for microMIPS jump instructions llvm-svn: 193623
2013-10-30 00:38:59 +08:00
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
2014-11-27 22:41:44 +08:00
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder) {
if (Value == 0)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(1));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
2014-11-27 22:41:44 +08:00
else if (Value == 0x7)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(-1));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
2014-11-27 22:41:44 +08:00
else
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(Value << 2));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
2014-11-27 22:41:44 +08:00
return MCDisassembler::Success;
}
[mips] Range check simm7. Summary: Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual encoding (it's a uimm7 except that 0x7f represents -1). Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18145 llvm-svn: 264056
2016-03-22 22:40:00 +08:00
static DecodeStatus DecodeLi16Imm(MCInst &Inst,
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
2014-11-27 22:41:44 +08:00
unsigned Value,
uint64_t Address,
const void *Decoder) {
if (Value == 0x7F)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(-1));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
2014-11-27 22:41:44 +08:00
else
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(Value));
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
2014-11-27 22:41:44 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions Differential Revision: http://reviews.llvm.org/D11178 llvm-svn: 247146
2015-09-09 21:55:45 +08:00
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder) {
Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
return MCDisassembler::Success;
}
[mips] Range check uimm6_lsl2. Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17291 llvm-svn: 263419
2016-03-14 19:16:56 +08:00
template <unsigned Bits, int Offset, int Scale>
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
uint64_t Address,
const void *Decoder) {
[mips][ias] Range check uimm2 operands and fix a bug this revealed. Summary: The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA (unlike the MSA version) failed to account for the off-by-one encoding of the immediate. The range is actually 1..4 rather than 0..3. Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14015 llvm-svn: 252295
2015-11-06 20:22:31 +08:00
Value &= ((1 << Bits) - 1);
[mips] Range check uimm6_lsl2. Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17291 llvm-svn: 263419
2016-03-14 19:16:56 +08:00
Value *= Scale;
[mips][ias] Range check uimm2 operands and fix a bug this revealed. Summary: The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA (unlike the MSA version) failed to account for the off-by-one encoding of the immediate. The range is actually 1..4 rather than 0..3. Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14015 llvm-svn: 252295
2015-11-06 20:22:31 +08:00
Inst.addOperand(MCOperand::createImm(Value + Offset));
[mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded. The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field. llvm-svn: 195004
2013-11-18 20:32:49 +08:00
return MCDisassembler::Success;
}
[mips] Range check simm7. Summary: Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual encoding (it's a uimm7 except that 0x7f represents -1). Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18145 llvm-svn: 264056
2016-03-22 22:40:00 +08:00
template <unsigned Bits, int Offset, int ScaleBy>
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
uint64_t Address,
const void *Decoder) {
int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
[mips] Range check simm4. Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16811 llvm-svn: 263220
2016-03-11 19:37:50 +08:00
Inst.addOperand(MCOperand::createImm(Imm + Offset));
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeInsSize(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
// First we need to grab the pos(lsb) from MCInst.
[mips] Implement the 'dins' aliases. Traditionally GAS has provided automatic selection between dins, dinsm and dinsu. Binutils also disassembles all instructions in that family as 'dins' rather than the actual instruction. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34877 llvm-svn: 313267
2017-09-14 23:17:50 +08:00
// This function only handles the 32 bit variants of ins, as dins
// variants are handled differently.
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
int Pos = Inst.getOperand(2).getImm();
[mips] Implement the 'dins' aliases. Traditionally GAS has provided automatic selection between dins, dinsm and dinsu. Binutils also disassembles all instructions in that family as 'dins' rather than the actual instruction. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34877 llvm-svn: 313267
2017-09-14 23:17:50 +08:00
int Size = (int) Insn - Pos + 1;
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips][mips64r6] Add addiupc, aluipc, and auipc Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 llvm-svn: 208858
2014-05-15 18:45:58 +08:00
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
[mips][mips64r6] Add addiupc, aluipc, and auipc Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 llvm-svn: 208858
2014-05-15 18:45:58 +08:00
return MCDisassembler::Success;
}
[mips][mips64r6] Add LDPC instruction Differential Revision: http://reviews.llvm.org/D3822 llvm-svn: 210460
2014-06-09 17:49:51 +08:00
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
[mips][mips64r6] Add LDPC instruction Differential Revision: http://reviews.llvm.org/D3822 llvm-svn: 210460
2014-06-09 17:49:51 +08:00
return MCDisassembler::Success;
}
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. llvm-svn: 223006
2014-12-01 19:12:04 +08:00
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
int32_t DecodedValue;
switch (Insn) {
case 0: DecodedValue = 256; break;
case 1: DecodedValue = 257; break;
case 510: DecodedValue = -258; break;
case 511: DecodedValue = -257; break;
default: DecodedValue = SignExtend32<9>(Insn); break;
}
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. llvm-svn: 223006
2014-12-01 19:12:04 +08:00
return MCDisassembler::Success;
}
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
// Insn must be >= 0, since it is unsigned that condition is always true.
assert(Insn < 16);
int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
255, 32768, 65535};
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. llvm-svn: 223006
2014-12-01 19:12:04 +08:00
return MCDisassembler::Success;
}
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
static DecodeStatus DecodeRegListOperand(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
[mips][microMIPS] Fix an issue with disassembling lwm32 instruction Fixed microMIPS disassembler crash on test case generated by llvm-mc-fuzzer. Differential Revision: http://reviews.llvm.org/D12881 llvm-svn: 247698
2015-09-15 23:21:27 +08:00
Mips::S6, Mips::S7, Mips::FP};
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
unsigned RegNum;
unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
[mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values. Summary: Some values of 'reglist' are reserved and cause the disassembler to read past the end of the Regs array. Treat lwm32's containing reserved values as invalid instructions. Reviewers: zoran.jovanovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12959 llvm-svn: 247990
2015-09-18 22:20:54 +08:00
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
// Empty register lists are not allowed.
if (RegLst == 0)
return MCDisassembler::Fail;
RegNum = RegLst & 0xf;
[mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values. Summary: Some values of 'reglist' are reserved and cause the disassembler to read past the end of the Regs array. Treat lwm32's containing reserved values as invalid instructions. Reviewers: zoran.jovanovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12959 llvm-svn: 247990
2015-09-18 22:20:54 +08:00
// RegLst values 10-15, and 26-31 are reserved.
if (RegNum > 9)
return MCDisassembler::Fail;
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
for (unsigned i = 0; i < RegNum; i++)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Regs[i]));
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
if (RegLst & 0x10)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::RA));
[mips][micromips] Implement SWM32 and LWM32 instructions Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
2014-11-20 00:44:02 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement SWM16 and LWM16 instructions Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
2014-11-28 02:28:59 +08:00
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
[mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
2015-11-12 21:21:33 +08:00
unsigned RegLst;
switch(Inst.getOpcode()) {
default:
RegLst = fieldFromInstruction(Insn, 4, 2);
break;
case Mips::LWM16_MMR6:
case Mips::SWM16_MMR6:
RegLst = fieldFromInstruction(Insn, 8, 2);
break;
}
[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16 Differential Revision: http://reviews.llvm.org/D7436 llvm-svn: 228683
2015-02-10 20:41:13 +08:00
unsigned RegNum = RegLst & 0x3;
[mips][microMIPS] Implement SWM16 and LWM16 instructions Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
2014-11-28 02:28:59 +08:00
[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16 Differential Revision: http://reviews.llvm.org/D7436 llvm-svn: 228683
2015-02-10 20:41:13 +08:00
for (unsigned i = 0; i <= RegNum; i++)
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Regs[i]));
[mips][microMIPS] Implement SWM16 and LWM16 instructions Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
2014-11-28 02:28:59 +08:00
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::RA));
[mips][microMIPS] Implement SWM16 and LWM16 instructions Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
2014-11-28 02:28:59 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement ADDIUPC instruction Differential Revision: http://reviews.llvm.org/D6582 llvm-svn: 226656
2015-01-21 20:10:11 +08:00
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
switch (RegPair) {
default:
return MCDisassembler::Fail;
case 0:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::A1));
Inst.addOperand(MCOperand::createReg(Mips::A2));
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
break;
case 1:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::A1));
Inst.addOperand(MCOperand::createReg(Mips::A3));
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
break;
case 2:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::A2));
Inst.addOperand(MCOperand::createReg(Mips::A3));
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
break;
case 3:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::A0));
Inst.addOperand(MCOperand::createReg(Mips::S5));
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
break;
case 4:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::A0));
Inst.addOperand(MCOperand::createReg(Mips::S6));
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
break;
case 5:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::A0));
Inst.addOperand(MCOperand::createReg(Mips::A1));
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
break;
case 6:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::A0));
Inst.addOperand(MCOperand::createReg(Mips::A2));
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
break;
case 7:
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
2015-05-14 02:37:00 +08:00
Inst.addOperand(MCOperand::createReg(Mips::A0));
Inst.addOperand(MCOperand::createReg(Mips::A3));
[mips][microMIPS] Implement movep instruction Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
2015-02-11 00:36:20 +08:00
break;
}
return MCDisassembler::Success;
}
[mips][microMIPS] Implement ADDIUPC instruction Differential Revision: http://reviews.llvm.org/D6582 llvm-svn: 226656
2015-01-21 20:10:11 +08:00
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
[mips] Fix some UB by shifting before sign-extending Avoid shifting a negative value by sign-extending after the shift. Fixes a couple of tests that were failing under ubsan. llvm-svn: 240381
2015-06-23 15:28:57 +08:00
Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
[mips][microMIPS] Implement ADDIUPC instruction Differential Revision: http://reviews.llvm.org/D6582 llvm-svn: 226656
2015-01-21 20:10:11 +08:00
return MCDisassembler::Success;
}
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
template <typename InsnType>
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
// We have:
// 0b000111 ttttt sssss iiiiiiiiiiiiiiii
// Invalid if rt == 0
// BGTZALC_MMR6 if rs == 0 && rt != 0
// BLTZALC_MMR6 if rs != 0 && rs == rt
// BLTUC_MMR6 if rs != 0 && rs != rt
InsnType Rt = fieldFromInstruction(insn, 21, 5);
InsnType Rs = fieldFromInstruction(insn, 16, 5);
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
InsnType Imm = 0;
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
bool HasRs = false;
bool HasRt = false;
if (Rt == 0)
return MCDisassembler::Fail;
else if (Rs == 0) {
MI.setOpcode(Mips::BGTZALC_MMR6);
HasRt = true;
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
}
else if (Rs == Rt) {
MI.setOpcode(Mips::BLTZALC_MMR6);
HasRs = true;
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
}
else {
MI.setOpcode(Mips::BLTUC_MMR6);
HasRs = true;
HasRt = true;
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
}
if (HasRs)
MI.addOperand(
MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
if (HasRt)
MI.addOperand(
MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
template <typename InsnType>
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
uint64_t Address,
const void *Decoder) {
// We have:
// 0b000110 ttttt sssss iiiiiiiiiiiiiiii
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
// Invalid if rt == 0
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
// BLEZALC_MMR6 if rs == 0 && rt != 0
// BGEZALC_MMR6 if rs == rt && rt != 0
// BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
InsnType Rt = fieldFromInstruction(insn, 21, 5);
InsnType Rs = fieldFromInstruction(insn, 16, 5);
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
InsnType Imm = 0;
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
bool HasRs = false;
if (Rt == 0)
return MCDisassembler::Fail;
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
else if (Rs == 0) {
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
MI.setOpcode(Mips::BLEZALC_MMR6);
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
}
else if (Rs == Rt) {
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
MI.setOpcode(Mips::BGEZALC_MMR6);
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
}
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
else {
HasRs = true;
MI.setOpcode(Mips::BGEUC_MMR6);
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
2016-08-22 20:17:59 +08:00
Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
2016-04-20 22:07:46 +08:00
}
if (HasRs)
MI.addOperand(
MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
MI.addOperand(
MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}