2016-05-02 23:25:49 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
2015-03-21 23:36:21 +08:00
|
|
|
; Test that the memchr library call simplifier works correctly.
|
|
|
|
; RUN: opt < %s -instcombine -S | FileCheck %s
|
|
|
|
|
[SimplifyLibCalls] Turn memchr(const, C, const) into a bitfield check.
strchr("123!", C) != nullptr is a common pattern to check if C is one
of 1, 2, 3 or !. If the largest element of the string is smaller than
the target's register size we can easily create a bitfield and just
do a simple test for set membership.
int foo(char C) { return strchr("123!", C) != nullptr; } now becomes
cmpl $64, %edi ## range check
sbbb %al, %al
movabsq $0xE000200000001, %rcx
btq %rdi, %rcx ## bit test
sbbb %cl, %cl
andb %al, %cl ## and the two conditions
andb $1, %cl
movzbl %cl, %eax ## returning an int
ret
(imho the backend should expand this into a series of branches, but
that's a different story)
The code is currently limited to bit fields that fit in a register, so
usually 64 or 32 bits. Sadly, this misses anything using alpha chars
or {}. This could be fixed by just emitting a i128 bit field, but that
can generate really ugly code so we have to find a better way. To some
degree this is also recreating switch lowering logic, but we can't
simply emit a switch instruction and thus change the CFG within
instcombine.
llvm-svn: 232902
2015-03-22 05:09:33 +08:00
|
|
|
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
|
2015-03-21 23:36:21 +08:00
|
|
|
|
|
|
|
@hello = constant [14 x i8] c"hello world\5Cn\00"
|
|
|
|
@hellonull = constant [14 x i8] c"hello\00world\5Cn\00"
|
|
|
|
@null = constant [1 x i8] zeroinitializer
|
[SimplifyLibCalls] Turn memchr(const, C, const) into a bitfield check.
strchr("123!", C) != nullptr is a common pattern to check if C is one
of 1, 2, 3 or !. If the largest element of the string is smaller than
the target's register size we can easily create a bitfield and just
do a simple test for set membership.
int foo(char C) { return strchr("123!", C) != nullptr; } now becomes
cmpl $64, %edi ## range check
sbbb %al, %al
movabsq $0xE000200000001, %rcx
btq %rdi, %rcx ## bit test
sbbb %cl, %cl
andb %al, %cl ## and the two conditions
andb $1, %cl
movzbl %cl, %eax ## returning an int
ret
(imho the backend should expand this into a series of branches, but
that's a different story)
The code is currently limited to bit fields that fit in a register, so
usually 64 or 32 bits. Sadly, this misses anything using alpha chars
or {}. This could be fixed by just emitting a i128 bit field, but that
can generate really ugly code so we have to find a better way. To some
degree this is also recreating switch lowering logic, but we can't
simply emit a switch instruction and thus change the CFG within
instcombine.
llvm-svn: 232902
2015-03-22 05:09:33 +08:00
|
|
|
@newlines = constant [3 x i8] c"\0D\0A\00"
|
|
|
|
@single = constant [2 x i8] c"\1F\00"
|
|
|
|
@spaces = constant [4 x i8] c" \0D\0A\00"
|
2015-03-22 06:04:26 +08:00
|
|
|
@negative = constant [3 x i8] c"\FF\FE\00"
|
2015-03-21 23:36:21 +08:00
|
|
|
@chp = global i8* zeroinitializer
|
|
|
|
|
|
|
|
declare i8* @memchr(i8*, i32, i32)
|
|
|
|
|
|
|
|
define void @test1() {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test1(
|
|
|
|
; CHECK-NEXT: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 6), i8** @chp, align 4
|
|
|
|
; CHECK-NEXT: ret void
|
|
|
|
;
|
2015-03-21 23:36:21 +08:00
|
|
|
%str = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
|
|
|
|
%dst = call i8* @memchr(i8* %str, i32 119, i32 14)
|
|
|
|
store i8* %dst, i8** @chp
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test2() {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test2(
|
|
|
|
; CHECK-NEXT: store i8* null, i8** @chp, align 4
|
|
|
|
; CHECK-NEXT: ret void
|
|
|
|
;
|
2015-03-21 23:36:21 +08:00
|
|
|
%str = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
|
|
|
|
%dst = call i8* @memchr(i8* %str, i32 119, i32 1)
|
|
|
|
store i8* %dst, i8** @chp
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test3() {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test3(
|
|
|
|
; CHECK-NEXT: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 13), i8** @chp, align 4
|
|
|
|
; CHECK-NEXT: ret void
|
|
|
|
;
|
2015-03-21 23:36:21 +08:00
|
|
|
%src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
|
|
|
|
%dst = call i8* @memchr(i8* %src, i32 0, i32 14)
|
|
|
|
store i8* %dst, i8** @chp
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test4(i32 %chr) {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test4(
|
|
|
|
; CHECK-NEXT: [[DST:%.*]] = call i8* @memchr(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 0), i32 %chr, i32 14)
|
|
|
|
; CHECK-NEXT: store i8* [[DST]], i8** @chp, align 4
|
|
|
|
; CHECK-NEXT: ret void
|
|
|
|
;
|
2015-03-21 23:36:21 +08:00
|
|
|
%src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
|
|
|
|
%dst = call i8* @memchr(i8* %src, i32 %chr, i32 14)
|
|
|
|
store i8* %dst, i8** @chp
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test5() {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test5(
|
|
|
|
; CHECK-NEXT: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 13), i8** @chp, align 4
|
|
|
|
; CHECK-NEXT: ret void
|
|
|
|
;
|
2015-03-21 23:36:21 +08:00
|
|
|
%src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
|
|
|
|
%dst = call i8* @memchr(i8* %src, i32 65280, i32 14)
|
|
|
|
store i8* %dst, i8** @chp
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test6() {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test6(
|
|
|
|
; CHECK-NEXT: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 6), i8** @chp, align 4
|
|
|
|
; CHECK-NEXT: ret void
|
|
|
|
;
|
2015-03-21 23:36:21 +08:00
|
|
|
%src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
|
|
|
|
; Overflow, but we still find the right thing.
|
|
|
|
%dst = call i8* @memchr(i8* %src, i32 119, i32 100)
|
|
|
|
store i8* %dst, i8** @chp
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test7() {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test7(
|
|
|
|
; CHECK-NEXT: store i8* null, i8** @chp, align 4
|
|
|
|
; CHECK-NEXT: ret void
|
|
|
|
;
|
2015-03-21 23:36:21 +08:00
|
|
|
%src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
|
|
|
|
; Overflow
|
|
|
|
%dst = call i8* @memchr(i8* %src, i32 120, i32 100)
|
|
|
|
store i8* %dst, i8** @chp
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test8() {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test8(
|
|
|
|
; CHECK-NEXT: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hellonull, i32 0, i32 6), i8** @chp, align 4
|
|
|
|
; CHECK-NEXT: ret void
|
|
|
|
;
|
2015-03-21 23:36:21 +08:00
|
|
|
%str = getelementptr [14 x i8], [14 x i8]* @hellonull, i32 0, i32 0
|
|
|
|
%dst = call i8* @memchr(i8* %str, i32 119, i32 14)
|
|
|
|
store i8* %dst, i8** @chp
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test9() {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test9(
|
|
|
|
; CHECK-NEXT: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hellonull, i32 0, i32 6), i8** @chp, align 4
|
|
|
|
; CHECK-NEXT: ret void
|
|
|
|
;
|
2015-03-21 23:36:21 +08:00
|
|
|
%str = getelementptr [14 x i8], [14 x i8]* @hellonull, i32 0, i32 2
|
|
|
|
%dst = call i8* @memchr(i8* %str, i32 119, i32 12)
|
|
|
|
store i8* %dst, i8** @chp
|
|
|
|
ret void
|
|
|
|
}
|
[SimplifyLibCalls] Turn memchr(const, C, const) into a bitfield check.
strchr("123!", C) != nullptr is a common pattern to check if C is one
of 1, 2, 3 or !. If the largest element of the string is smaller than
the target's register size we can easily create a bitfield and just
do a simple test for set membership.
int foo(char C) { return strchr("123!", C) != nullptr; } now becomes
cmpl $64, %edi ## range check
sbbb %al, %al
movabsq $0xE000200000001, %rcx
btq %rdi, %rcx ## bit test
sbbb %cl, %cl
andb %al, %cl ## and the two conditions
andb $1, %cl
movzbl %cl, %eax ## returning an int
ret
(imho the backend should expand this into a series of branches, but
that's a different story)
The code is currently limited to bit fields that fit in a register, so
usually 64 or 32 bits. Sadly, this misses anything using alpha chars
or {}. This could be fixed by just emitting a i128 bit field, but that
can generate really ugly code so we have to find a better way. To some
degree this is also recreating switch lowering logic, but we can't
simply emit a switch instruction and thus change the CFG within
instcombine.
llvm-svn: 232902
2015-03-22 05:09:33 +08:00
|
|
|
|
|
|
|
define void @test10() {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test10(
|
|
|
|
; CHECK-NEXT: store i8* null, i8** @chp, align 4
|
|
|
|
; CHECK-NEXT: ret void
|
|
|
|
;
|
[SimplifyLibCalls] Turn memchr(const, C, const) into a bitfield check.
strchr("123!", C) != nullptr is a common pattern to check if C is one
of 1, 2, 3 or !. If the largest element of the string is smaller than
the target's register size we can easily create a bitfield and just
do a simple test for set membership.
int foo(char C) { return strchr("123!", C) != nullptr; } now becomes
cmpl $64, %edi ## range check
sbbb %al, %al
movabsq $0xE000200000001, %rcx
btq %rdi, %rcx ## bit test
sbbb %cl, %cl
andb %al, %cl ## and the two conditions
andb $1, %cl
movzbl %cl, %eax ## returning an int
ret
(imho the backend should expand this into a series of branches, but
that's a different story)
The code is currently limited to bit fields that fit in a register, so
usually 64 or 32 bits. Sadly, this misses anything using alpha chars
or {}. This could be fixed by just emitting a i128 bit field, but that
can generate really ugly code so we have to find a better way. To some
degree this is also recreating switch lowering logic, but we can't
simply emit a switch instruction and thus change the CFG within
instcombine.
llvm-svn: 232902
2015-03-22 05:09:33 +08:00
|
|
|
%str = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
|
|
|
|
%dst = call i8* @memchr(i8* %str, i32 119, i32 6)
|
|
|
|
store i8* %dst, i8** @chp
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
; Check transformation memchr("\r\n", C, 2) != nullptr -> (C & 9216) != 0
|
|
|
|
define i1 @test11(i32 %C) {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test11(
|
|
|
|
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %C to i16
|
|
|
|
; CHECK-NEXT: [[MEMCHR_BOUNDS:%.*]] = icmp ult i16 [[TMP1]], 16
|
|
|
|
; CHECK-NEXT: [[TMP2:%.*]] = shl i16 1, [[TMP1]]
|
|
|
|
; CHECK-NEXT: [[TMP3:%.*]] = and i16 [[TMP2]], 9216
|
|
|
|
; CHECK-NEXT: [[MEMCHR_BITS:%.*]] = icmp ne i16 [[TMP3]], 0
|
|
|
|
; CHECK-NEXT: [[MEMCHR:%.*]] = and i1 [[MEMCHR:%.*]].bounds, [[MEMCHR:%.*]].bits
|
|
|
|
; CHECK-NEXT: ret i1 [[MEMCHR]]
|
|
|
|
;
|
[SimplifyLibCalls] Turn memchr(const, C, const) into a bitfield check.
strchr("123!", C) != nullptr is a common pattern to check if C is one
of 1, 2, 3 or !. If the largest element of the string is smaller than
the target's register size we can easily create a bitfield and just
do a simple test for set membership.
int foo(char C) { return strchr("123!", C) != nullptr; } now becomes
cmpl $64, %edi ## range check
sbbb %al, %al
movabsq $0xE000200000001, %rcx
btq %rdi, %rcx ## bit test
sbbb %cl, %cl
andb %al, %cl ## and the two conditions
andb $1, %cl
movzbl %cl, %eax ## returning an int
ret
(imho the backend should expand this into a series of branches, but
that's a different story)
The code is currently limited to bit fields that fit in a register, so
usually 64 or 32 bits. Sadly, this misses anything using alpha chars
or {}. This could be fixed by just emitting a i128 bit field, but that
can generate really ugly code so we have to find a better way. To some
degree this is also recreating switch lowering logic, but we can't
simply emit a switch instruction and thus change the CFG within
instcombine.
llvm-svn: 232902
2015-03-22 05:09:33 +08:00
|
|
|
%dst = call i8* @memchr(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @newlines, i64 0, i64 0), i32 %C, i32 2)
|
|
|
|
%cmp = icmp ne i8* %dst, null
|
|
|
|
ret i1 %cmp
|
|
|
|
}
|
|
|
|
|
|
|
|
; No 64 bits here
|
|
|
|
define i1 @test12(i32 %C) {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test12(
|
|
|
|
; CHECK-NEXT: [[DST:%.*]] = call i8* @memchr(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @spaces, i32 0, i32 0), i32 %C, i32 3)
|
|
|
|
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8* [[DST]], null
|
|
|
|
; CHECK-NEXT: ret i1 [[CMP]]
|
|
|
|
;
|
[SimplifyLibCalls] Turn memchr(const, C, const) into a bitfield check.
strchr("123!", C) != nullptr is a common pattern to check if C is one
of 1, 2, 3 or !. If the largest element of the string is smaller than
the target's register size we can easily create a bitfield and just
do a simple test for set membership.
int foo(char C) { return strchr("123!", C) != nullptr; } now becomes
cmpl $64, %edi ## range check
sbbb %al, %al
movabsq $0xE000200000001, %rcx
btq %rdi, %rcx ## bit test
sbbb %cl, %cl
andb %al, %cl ## and the two conditions
andb $1, %cl
movzbl %cl, %eax ## returning an int
ret
(imho the backend should expand this into a series of branches, but
that's a different story)
The code is currently limited to bit fields that fit in a register, so
usually 64 or 32 bits. Sadly, this misses anything using alpha chars
or {}. This could be fixed by just emitting a i128 bit field, but that
can generate really ugly code so we have to find a better way. To some
degree this is also recreating switch lowering logic, but we can't
simply emit a switch instruction and thus change the CFG within
instcombine.
llvm-svn: 232902
2015-03-22 05:09:33 +08:00
|
|
|
%dst = call i8* @memchr(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @spaces, i64 0, i64 0), i32 %C, i32 3)
|
|
|
|
%cmp = icmp ne i8* %dst, null
|
|
|
|
ret i1 %cmp
|
|
|
|
}
|
|
|
|
|
|
|
|
define i1 @test13(i32 %C) {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test13(
|
|
|
|
; CHECK-NEXT: [[MEMCHR_BOUNDS:%.*]] = icmp ult i32 %C, 32
|
|
|
|
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 1, %C
|
|
|
|
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -2147483647
|
|
|
|
; CHECK-NEXT: [[MEMCHR_BITS:%.*]] = icmp ne i32 [[TMP2]], 0
|
|
|
|
; CHECK-NEXT: [[MEMCHR:%.*]] = and i1 [[MEMCHR:%.*]].bounds, [[MEMCHR:%.*]].bits
|
|
|
|
; CHECK-NEXT: ret i1 [[MEMCHR]]
|
|
|
|
;
|
[SimplifyLibCalls] Turn memchr(const, C, const) into a bitfield check.
strchr("123!", C) != nullptr is a common pattern to check if C is one
of 1, 2, 3 or !. If the largest element of the string is smaller than
the target's register size we can easily create a bitfield and just
do a simple test for set membership.
int foo(char C) { return strchr("123!", C) != nullptr; } now becomes
cmpl $64, %edi ## range check
sbbb %al, %al
movabsq $0xE000200000001, %rcx
btq %rdi, %rcx ## bit test
sbbb %cl, %cl
andb %al, %cl ## and the two conditions
andb $1, %cl
movzbl %cl, %eax ## returning an int
ret
(imho the backend should expand this into a series of branches, but
that's a different story)
The code is currently limited to bit fields that fit in a register, so
usually 64 or 32 bits. Sadly, this misses anything using alpha chars
or {}. This could be fixed by just emitting a i128 bit field, but that
can generate really ugly code so we have to find a better way. To some
degree this is also recreating switch lowering logic, but we can't
simply emit a switch instruction and thus change the CFG within
instcombine.
llvm-svn: 232902
2015-03-22 05:09:33 +08:00
|
|
|
%dst = call i8* @memchr(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @single, i64 0, i64 0), i32 %C, i32 2)
|
|
|
|
%cmp = icmp ne i8* %dst, null
|
|
|
|
ret i1 %cmp
|
|
|
|
}
|
|
|
|
|
|
|
|
define i1 @test14(i32 %C) {
|
2016-05-02 23:25:49 +08:00
|
|
|
; CHECK-LABEL: @test14(
|
|
|
|
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 %C, 31
|
|
|
|
; CHECK-NEXT: ret i1 [[TMP1]]
|
|
|
|
;
|
[SimplifyLibCalls] Turn memchr(const, C, const) into a bitfield check.
strchr("123!", C) != nullptr is a common pattern to check if C is one
of 1, 2, 3 or !. If the largest element of the string is smaller than
the target's register size we can easily create a bitfield and just
do a simple test for set membership.
int foo(char C) { return strchr("123!", C) != nullptr; } now becomes
cmpl $64, %edi ## range check
sbbb %al, %al
movabsq $0xE000200000001, %rcx
btq %rdi, %rcx ## bit test
sbbb %cl, %cl
andb %al, %cl ## and the two conditions
andb $1, %cl
movzbl %cl, %eax ## returning an int
ret
(imho the backend should expand this into a series of branches, but
that's a different story)
The code is currently limited to bit fields that fit in a register, so
usually 64 or 32 bits. Sadly, this misses anything using alpha chars
or {}. This could be fixed by just emitting a i128 bit field, but that
can generate really ugly code so we have to find a better way. To some
degree this is also recreating switch lowering logic, but we can't
simply emit a switch instruction and thus change the CFG within
instcombine.
llvm-svn: 232902
2015-03-22 05:09:33 +08:00
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%dst = call i8* @memchr(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @single, i64 0, i64 0), i32 %C, i32 1)
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%cmp = icmp ne i8* %dst, null
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ret i1 %cmp
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}
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2015-03-22 06:04:26 +08:00
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define i1 @test15(i32 %C) {
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2016-05-02 23:25:49 +08:00
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; CHECK-LABEL: @test15(
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; CHECK-NEXT: [[DST:%.*]] = call i8* @memchr(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @negative, i32 0, i32 0), i32 %C, i32 3)
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8* [[DST]], null
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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2015-03-22 06:04:26 +08:00
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%dst = call i8* @memchr(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @negative, i64 0, i64 0), i32 %C, i32 3)
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%cmp = icmp ne i8* %dst, null
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ret i1 %cmp
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}
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