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llvm-project/llvm/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll

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Reenabling this test with REQUIRES: Asserts llvm-svn: 133132
2011-06-16 09:34:41 +08:00
; RUN: llc < %s -march=x86-64 -stress-sched | FileCheck %s
lit support for REQUIRES: asserts. Take #2. Don't piggyback on the existing config.build_mode. Instead, define a new lit feature for each build feature we need (currently just "asserts"). Teach both autoconf'd and cmake'd Makefiles to define this feature within test/lit.site.cfg. This doesn't require any lit harness changes and should be more robust across build systems. llvm-svn: 133664
2011-06-23 07:23:19 +08:00
; REQUIRES: asserts
Added -stress-sched flag in the Asserts build. Added a test case for handling physreg aliases during pre-RA-sched. llvm-svn: 133063
2011-06-16 01:16:12 +08:00
; Test interference between physreg aliases during preRAsched.
; mul wants an operand in AL, but call clobbers it.
define i8 @f(i8 %v1, i8 %v2) nounwind {
entry:
; CHECK: callq
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; CHECK: movl %{{.*}}, %eax
Added -stress-sched flag in the Asserts build. Added a test case for handling physreg aliases during pre-RA-sched. llvm-svn: 133063
2011-06-16 01:16:12 +08:00
; CHECK: mulb
; CHECK: mulb
%rval = tail call i8 @bar() nounwind
%m1 = mul i8 %v1, %v2
%m2 = mul i8 %m1, %rval
ret i8 %m2
}
declare i8 @bar()