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llvm-project/llvm/test/MC/AArch64/arm64-spsel-sysreg.s

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[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. llvm-svn: 205875
2014-04-09 22:43:06 +08:00
// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s
// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
msr SPSel, #0
msr SPSel, x0
msr DAIFSet, #0
msr ESR_EL1, x0
mrs x0, SPSel
mrs x0, ESR_EL1
AArch64: TableGenerate system instruction operands. The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
2016-07-06 05:23:04 +08:00
// CHECK: msr SPSel, #0 // encoding: [0xbf,0x40,0x00,0xd5]
// CHECK: msr SPSel, x0 // encoding: [0x00,0x42,0x18,0xd5]
// CHECK: msr DAIFSet, #0 // encoding: [0xdf,0x40,0x03,0xd5]
[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. llvm-svn: 205875
2014-04-09 22:43:06 +08:00
// CHECK: msr ESR_EL1, x0 // encoding: [0x00,0x52,0x18,0xd5]
AArch64: TableGenerate system instruction operands. The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
2016-07-06 05:23:04 +08:00
// CHECK: mrs x0, SPSel // encoding: [0x00,0x42,0x38,0xd5]
[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. llvm-svn: 205875
2014-04-09 22:43:06 +08:00
// CHECK: mrs x0, ESR_EL1 // encoding: [0x00,0x52,0x38,0xd5]
msr DAIFSet, x0
msr ESR_EL1, #0
mrs x0, DAIFSet
AArch64/ARM64: produce more informative diagnostic assembling some immediates No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
2014-05-06 19:18:53 +08:00
// CHECK-ERRORS: error: immediate must be an integer in range [0, 15]
[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. llvm-svn: 205875
2014-04-09 22:43:06 +08:00
// CHECK-ERRORS: error: invalid operand for instruction
AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests. llvm-svn: 207667
2014-05-01 00:13:20 +08:00
// CHECK-ERRORS: error: expected readable system register