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llvm-project/llvm/test/CodeGen/X86/aes-schedule.ll

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[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+aes | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
[X89] Explicitly enable aes in aes-schedule.ll to fix failures after r341861. llvm-svn: 341868
2018-09-11 05:49:01 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=slm -mattr=+aes | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=goldmont -mattr=+aes | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=sandybridge -mattr=+aes,-avx | FileCheck %s --check-prefixes=CHECK,SANDY-SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=sandybridge -mattr=+aes,-avx2 | FileCheck %s --check-prefixes=CHECK,SANDY
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=ivybridge -mattr=+aes,-avx | FileCheck %s --check-prefixes=CHECK,SANDY-SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=ivybridge -mattr=+aes,-avx2 | FileCheck %s --check-prefixes=CHECK,SANDY
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell -mattr=+aes,-avx | FileCheck %s --check-prefixes=CHECK,HASWELL-SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell -mattr=+aes,-avx2 | FileCheck %s --check-prefixes=CHECK,HASWELL
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=broadwell -mattr=+aes,-avx | FileCheck %s --check-prefixes=CHECK,BROADWELL-SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=broadwell -mattr=+aes,-avx2 | FileCheck %s --check-prefixes=CHECK,BROADWELL
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake -mattr=+aes,-avx | FileCheck %s --check-prefixes=CHECK,SKYLAKE-SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake -mattr=+aes,-avx2 | FileCheck %s --check-prefixes=CHECK,SKYLAKE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skx -mattr=+aes,-avx | FileCheck %s --check-prefixes=CHECK,SKX-SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skx -mattr=+aes,-avx2 | FileCheck %s --check-prefixes=CHECK,SKX
[NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler model Adding the baseline tests in a preparatory NFC commit, so that the actual commit shows the *diff*. Yes, i'm aware that a few of these codegen-based sched tests are testing wrong instructions, i will fix that afterwards. For https://reviews.llvm.org/D52779 llvm-svn: 345462
2018-10-28 04:36:11 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+aes,-avx | FileCheck %s --check-prefixes=CHECK,BDVER2-SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+avx -mattr=+aes,-avx2 | FileCheck %s --check-prefixes=CHECK,BDVER2
[X89] Explicitly enable aes in aes-schedule.ll to fix failures after r341861. llvm-svn: 341868
2018-09-11 05:49:01 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 -mattr=+aes,-avx | FileCheck %s --check-prefixes=CHECK,BTVER2-SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 -mattr=+aes,-avx2 | FileCheck %s --check-prefixes=CHECK,BTVER2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 -mattr=+aes,-avx | FileCheck %s --check-prefixes=CHECK,ZNVER1-SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 -mattr=+aes,-avx2 | FileCheck %s --check-prefixes=CHECK,ZNVER1
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
define <2 x i64> @test_aesdec(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
; GENERIC-LABEL: test_aesdec:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; GENERIC-NEXT: aesdec %xmm1, %xmm0 # sched: [7:1.00]
; GENERIC-NEXT: aesdec (%rdi), %xmm0 # sched: [13:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SLM-LABEL: test_aesdec:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SLM-NEXT: aesdec %xmm1, %xmm0 # sched: [8:5.00]
; SLM-NEXT: aesdec (%rdi), %xmm0 # sched: [8:5.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SANDY-SSE-LABEL: test_aesdec:
; SANDY-SSE: # %bb.0:
; SANDY-SSE-NEXT: aesdec %xmm1, %xmm0 # sched: [7:1.00]
; SANDY-SSE-NEXT: aesdec (%rdi), %xmm0 # sched: [13:1.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-LABEL: test_aesdec:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
; SANDY-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; HASWELL-SSE-LABEL: test_aesdec:
; HASWELL-SSE: # %bb.0:
; HASWELL-SSE-NEXT: aesdec %xmm1, %xmm0 # sched: [7:1.00]
; HASWELL-SSE-NEXT: aesdec (%rdi), %xmm0 # sched: [13:1.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-LABEL: test_aesdec:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BROADWELL-SSE-LABEL: test_aesdec:
; BROADWELL-SSE: # %bb.0:
; BROADWELL-SSE-NEXT: aesdec %xmm1, %xmm0 # sched: [7:1.00]
; BROADWELL-SSE-NEXT: aesdec (%rdi), %xmm0 # sched: [12:1.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-LABEL: test_aesdec:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
[X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU. Adding the scheduling information for the Browadwell (BDW) CPU target. This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target. We used the scheduling information retrieved from the Broadwell architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction. The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175. Performance fluctuations may be expected due to code alignment effects. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D39054 Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01 llvm-svn: 316492
2017-10-25 04:19:47 +08:00
; BROADWELL-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [12:1.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKYLAKE-SSE-LABEL: test_aesdec:
; SKYLAKE-SSE: # %bb.0:
; SKYLAKE-SSE-NEXT: aesdec %xmm1, %xmm0 # sched: [4:1.00]
; SKYLAKE-SSE-NEXT: aesdec (%rdi), %xmm0 # sched: [10:1.00]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
; SKYLAKE-LABEL: test_aesdec:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86][Skylake] Adding the scheduling information for the SkylakeClient target This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879. Please expect some performance fluctuations due to code alignment effects. Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena Differential Revision: https://reviews.llvm.org/D37294 llvm-svn: 313613
2017-09-19 14:19:27 +08:00
; SKYLAKE-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
[X86][SKL] Updated scheduling information for the SkylakeClient target Updated the scheduling information for the SkylakeClient target with the following changes: 1. regrouped the instructions after adding load and store latencies. 2. regrouped the instructions after adding identified missing ports in several groups. The changes were made after revisiting the latencies impact of all the load and store uOps. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D38727 Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f llvm-svn: 315978
2017-10-17 14:47:04 +08:00
; SKYLAKE-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKX-SSE-LABEL: test_aesdec:
; SKX-SSE: # %bb.0:
; SKX-SSE-NEXT: aesdec %xmm1, %xmm0 # sched: [4:1.00]
; SKX-SSE-NEXT: aesdec (%rdi), %xmm0 # sched: [10:1.00]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_aesdec:
; SKX: # %bb.0:
; SKX-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
; SKX-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
[NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler model Adding the baseline tests in a preparatory NFC commit, so that the actual commit shows the *diff*. Yes, i'm aware that a few of these codegen-based sched tests are testing wrong instructions, i will fix that afterwards. For https://reviews.llvm.org/D52779 llvm-svn: 345462
2018-10-28 04:36:11 +08:00
; BDVER2-SSE-LABEL: test_aesdec:
; BDVER2-SSE: # %bb.0:
; BDVER2-SSE-NEXT: aesdec %xmm1, %xmm0 # sched: [7:1.00]
; BDVER2-SSE-NEXT: aesdec (%rdi), %xmm0 # sched: [13:1.00]
; BDVER2-SSE-NEXT: retq # sched: [1:1.00]
;
; BDVER2-LABEL: test_aesdec:
; BDVER2: # %bb.0:
; BDVER2-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
; BDVER2-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; BDVER2-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BTVER2-SSE-LABEL: test_aesdec:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: aesdec %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: aesdec (%rdi), %xmm0 # sched: [8:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-LABEL: test_aesdec:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; ZNVER1-SSE-LABEL: test_aesdec:
; ZNVER1-SSE: # %bb.0:
; ZNVER1-SSE-NEXT: aesdec %xmm1, %xmm0 # sched: [4:0.50]
; ZNVER1-SSE-NEXT: aesdec (%rdi), %xmm0 # sched: [11:0.50]
; ZNVER1-SSE-NEXT: retq # sched: [1:0.50]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-LABEL: test_aesdec:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [11:0.50]
AMD family 17h (znver1) scheduler model update. Summary: This patch enables the following: 1) Regex based Instruction itineraries for integer instructions. 2) The instructions are grouped as per the nature of the instructions (move, arithmetic, logic, Misc, Control Transfer). 3) FP instructions and their itineraries are added which includes values for SSE4A, BMI, BMI2 and SHA instructions. Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36617 llvm-svn: 312237
2017-08-31 20:38:35 +08:00
; ZNVER1-NEXT: retq # sched: [1:0.50]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
%1 = load <2 x i64>, <2 x i64> *%a2, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %a0, <2 x i64> %a1)
%3 = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %2, <2 x i64> %1)
ret <2 x i64> %3
}
declare <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64>, <2 x i64>)
define <2 x i64> @test_aesdeclast(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
; GENERIC-LABEL: test_aesdeclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; GENERIC-NEXT: aesdeclast %xmm1, %xmm0 # sched: [7:1.00]
; GENERIC-NEXT: aesdeclast (%rdi), %xmm0 # sched: [13:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SLM-LABEL: test_aesdeclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SLM-NEXT: aesdeclast %xmm1, %xmm0 # sched: [8:5.00]
; SLM-NEXT: aesdeclast (%rdi), %xmm0 # sched: [8:5.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SANDY-SSE-LABEL: test_aesdeclast:
; SANDY-SSE: # %bb.0:
; SANDY-SSE-NEXT: aesdeclast %xmm1, %xmm0 # sched: [7:1.00]
; SANDY-SSE-NEXT: aesdeclast (%rdi), %xmm0 # sched: [13:1.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-LABEL: test_aesdeclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
; SANDY-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; HASWELL-SSE-LABEL: test_aesdeclast:
; HASWELL-SSE: # %bb.0:
; HASWELL-SSE-NEXT: aesdeclast %xmm1, %xmm0 # sched: [7:1.00]
; HASWELL-SSE-NEXT: aesdeclast (%rdi), %xmm0 # sched: [13:1.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-LABEL: test_aesdeclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BROADWELL-SSE-LABEL: test_aesdeclast:
; BROADWELL-SSE: # %bb.0:
; BROADWELL-SSE-NEXT: aesdeclast %xmm1, %xmm0 # sched: [7:1.00]
; BROADWELL-SSE-NEXT: aesdeclast (%rdi), %xmm0 # sched: [12:1.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-LABEL: test_aesdeclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
[X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU. Adding the scheduling information for the Browadwell (BDW) CPU target. This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target. We used the scheduling information retrieved from the Broadwell architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction. The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175. Performance fluctuations may be expected due to code alignment effects. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D39054 Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01 llvm-svn: 316492
2017-10-25 04:19:47 +08:00
; BROADWELL-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [12:1.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKYLAKE-SSE-LABEL: test_aesdeclast:
; SKYLAKE-SSE: # %bb.0:
; SKYLAKE-SSE-NEXT: aesdeclast %xmm1, %xmm0 # sched: [4:1.00]
; SKYLAKE-SSE-NEXT: aesdeclast (%rdi), %xmm0 # sched: [10:1.00]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
; SKYLAKE-LABEL: test_aesdeclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86][Skylake] Adding the scheduling information for the SkylakeClient target This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879. Please expect some performance fluctuations due to code alignment effects. Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena Differential Revision: https://reviews.llvm.org/D37294 llvm-svn: 313613
2017-09-19 14:19:27 +08:00
; SKYLAKE-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
[X86][SKL] Updated scheduling information for the SkylakeClient target Updated the scheduling information for the SkylakeClient target with the following changes: 1. regrouped the instructions after adding load and store latencies. 2. regrouped the instructions after adding identified missing ports in several groups. The changes were made after revisiting the latencies impact of all the load and store uOps. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D38727 Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f llvm-svn: 315978
2017-10-17 14:47:04 +08:00
; SKYLAKE-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKX-SSE-LABEL: test_aesdeclast:
; SKX-SSE: # %bb.0:
; SKX-SSE-NEXT: aesdeclast %xmm1, %xmm0 # sched: [4:1.00]
; SKX-SSE-NEXT: aesdeclast (%rdi), %xmm0 # sched: [10:1.00]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_aesdeclast:
; SKX: # %bb.0:
; SKX-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
; SKX-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
[NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler model Adding the baseline tests in a preparatory NFC commit, so that the actual commit shows the *diff*. Yes, i'm aware that a few of these codegen-based sched tests are testing wrong instructions, i will fix that afterwards. For https://reviews.llvm.org/D52779 llvm-svn: 345462
2018-10-28 04:36:11 +08:00
; BDVER2-SSE-LABEL: test_aesdeclast:
; BDVER2-SSE: # %bb.0:
; BDVER2-SSE-NEXT: aesdeclast %xmm1, %xmm0 # sched: [7:1.00]
; BDVER2-SSE-NEXT: aesdeclast (%rdi), %xmm0 # sched: [13:1.00]
; BDVER2-SSE-NEXT: retq # sched: [1:1.00]
;
; BDVER2-LABEL: test_aesdeclast:
; BDVER2: # %bb.0:
; BDVER2-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
; BDVER2-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; BDVER2-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BTVER2-SSE-LABEL: test_aesdeclast:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: aesdeclast %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: aesdeclast (%rdi), %xmm0 # sched: [8:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-LABEL: test_aesdeclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; ZNVER1-SSE-LABEL: test_aesdeclast:
; ZNVER1-SSE: # %bb.0:
; ZNVER1-SSE-NEXT: aesdeclast %xmm1, %xmm0 # sched: [4:0.50]
; ZNVER1-SSE-NEXT: aesdeclast (%rdi), %xmm0 # sched: [11:0.50]
; ZNVER1-SSE-NEXT: retq # sched: [1:0.50]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-LABEL: test_aesdeclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [11:0.50]
AMD family 17h (znver1) scheduler model update. Summary: This patch enables the following: 1) Regex based Instruction itineraries for integer instructions. 2) The instructions are grouped as per the nature of the instructions (move, arithmetic, logic, Misc, Control Transfer). 3) FP instructions and their itineraries are added which includes values for SSE4A, BMI, BMI2 and SHA instructions. Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36617 llvm-svn: 312237
2017-08-31 20:38:35 +08:00
; ZNVER1-NEXT: retq # sched: [1:0.50]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
%1 = load <2 x i64>, <2 x i64> *%a2, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %a0, <2 x i64> %a1)
%3 = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %2, <2 x i64> %1)
ret <2 x i64> %3
}
declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>)
define <2 x i64> @test_aesenc(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
; GENERIC-LABEL: test_aesenc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; GENERIC-NEXT: aesenc %xmm1, %xmm0 # sched: [7:1.00]
; GENERIC-NEXT: aesenc (%rdi), %xmm0 # sched: [13:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SLM-LABEL: test_aesenc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SLM-NEXT: aesenc %xmm1, %xmm0 # sched: [8:5.00]
; SLM-NEXT: aesenc (%rdi), %xmm0 # sched: [8:5.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SANDY-SSE-LABEL: test_aesenc:
; SANDY-SSE: # %bb.0:
; SANDY-SSE-NEXT: aesenc %xmm1, %xmm0 # sched: [7:1.00]
; SANDY-SSE-NEXT: aesenc (%rdi), %xmm0 # sched: [13:1.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-LABEL: test_aesenc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
; SANDY-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; HASWELL-SSE-LABEL: test_aesenc:
; HASWELL-SSE: # %bb.0:
; HASWELL-SSE-NEXT: aesenc %xmm1, %xmm0 # sched: [7:1.00]
; HASWELL-SSE-NEXT: aesenc (%rdi), %xmm0 # sched: [13:1.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-LABEL: test_aesenc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BROADWELL-SSE-LABEL: test_aesenc:
; BROADWELL-SSE: # %bb.0:
; BROADWELL-SSE-NEXT: aesenc %xmm1, %xmm0 # sched: [7:1.00]
; BROADWELL-SSE-NEXT: aesenc (%rdi), %xmm0 # sched: [12:1.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-LABEL: test_aesenc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
[X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU. Adding the scheduling information for the Browadwell (BDW) CPU target. This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target. We used the scheduling information retrieved from the Broadwell architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction. The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175. Performance fluctuations may be expected due to code alignment effects. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D39054 Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01 llvm-svn: 316492
2017-10-25 04:19:47 +08:00
; BROADWELL-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [12:1.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKYLAKE-SSE-LABEL: test_aesenc:
; SKYLAKE-SSE: # %bb.0:
; SKYLAKE-SSE-NEXT: aesenc %xmm1, %xmm0 # sched: [4:1.00]
; SKYLAKE-SSE-NEXT: aesenc (%rdi), %xmm0 # sched: [10:1.00]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
; SKYLAKE-LABEL: test_aesenc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86][Skylake] Adding the scheduling information for the SkylakeClient target This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879. Please expect some performance fluctuations due to code alignment effects. Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena Differential Revision: https://reviews.llvm.org/D37294 llvm-svn: 313613
2017-09-19 14:19:27 +08:00
; SKYLAKE-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
[X86][SKL] Updated scheduling information for the SkylakeClient target Updated the scheduling information for the SkylakeClient target with the following changes: 1. regrouped the instructions after adding load and store latencies. 2. regrouped the instructions after adding identified missing ports in several groups. The changes were made after revisiting the latencies impact of all the load and store uOps. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D38727 Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f llvm-svn: 315978
2017-10-17 14:47:04 +08:00
; SKYLAKE-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKX-SSE-LABEL: test_aesenc:
; SKX-SSE: # %bb.0:
; SKX-SSE-NEXT: aesenc %xmm1, %xmm0 # sched: [4:1.00]
; SKX-SSE-NEXT: aesenc (%rdi), %xmm0 # sched: [10:1.00]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_aesenc:
; SKX: # %bb.0:
; SKX-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
; SKX-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
[NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler model Adding the baseline tests in a preparatory NFC commit, so that the actual commit shows the *diff*. Yes, i'm aware that a few of these codegen-based sched tests are testing wrong instructions, i will fix that afterwards. For https://reviews.llvm.org/D52779 llvm-svn: 345462
2018-10-28 04:36:11 +08:00
; BDVER2-SSE-LABEL: test_aesenc:
; BDVER2-SSE: # %bb.0:
; BDVER2-SSE-NEXT: aesenc %xmm1, %xmm0 # sched: [7:1.00]
; BDVER2-SSE-NEXT: aesenc (%rdi), %xmm0 # sched: [13:1.00]
; BDVER2-SSE-NEXT: retq # sched: [1:1.00]
;
; BDVER2-LABEL: test_aesenc:
; BDVER2: # %bb.0:
; BDVER2-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
; BDVER2-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; BDVER2-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BTVER2-SSE-LABEL: test_aesenc:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: aesenc %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: aesenc (%rdi), %xmm0 # sched: [8:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-LABEL: test_aesenc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; ZNVER1-SSE-LABEL: test_aesenc:
; ZNVER1-SSE: # %bb.0:
; ZNVER1-SSE-NEXT: aesenc %xmm1, %xmm0 # sched: [4:0.50]
; ZNVER1-SSE-NEXT: aesenc (%rdi), %xmm0 # sched: [11:0.50]
; ZNVER1-SSE-NEXT: retq # sched: [1:0.50]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-LABEL: test_aesenc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [11:0.50]
AMD family 17h (znver1) scheduler model update. Summary: This patch enables the following: 1) Regex based Instruction itineraries for integer instructions. 2) The instructions are grouped as per the nature of the instructions (move, arithmetic, logic, Misc, Control Transfer). 3) FP instructions and their itineraries are added which includes values for SSE4A, BMI, BMI2 and SHA instructions. Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36617 llvm-svn: 312237
2017-08-31 20:38:35 +08:00
; ZNVER1-NEXT: retq # sched: [1:0.50]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
%1 = load <2 x i64>, <2 x i64> *%a2, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %a0, <2 x i64> %a1)
%3 = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %2, <2 x i64> %1)
ret <2 x i64> %3
}
declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>)
define <2 x i64> @test_aesenclast(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
; GENERIC-LABEL: test_aesenclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; GENERIC-NEXT: aesenclast %xmm1, %xmm0 # sched: [7:1.00]
; GENERIC-NEXT: aesenclast (%rdi), %xmm0 # sched: [13:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SLM-LABEL: test_aesenclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SLM-NEXT: aesenclast %xmm1, %xmm0 # sched: [8:5.00]
; SLM-NEXT: aesenclast (%rdi), %xmm0 # sched: [8:5.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SANDY-SSE-LABEL: test_aesenclast:
; SANDY-SSE: # %bb.0:
; SANDY-SSE-NEXT: aesenclast %xmm1, %xmm0 # sched: [7:1.00]
; SANDY-SSE-NEXT: aesenclast (%rdi), %xmm0 # sched: [13:1.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-LABEL: test_aesenclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
; SANDY-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; HASWELL-SSE-LABEL: test_aesenclast:
; HASWELL-SSE: # %bb.0:
; HASWELL-SSE-NEXT: aesenclast %xmm1, %xmm0 # sched: [7:1.00]
; HASWELL-SSE-NEXT: aesenclast (%rdi), %xmm0 # sched: [13:1.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-LABEL: test_aesenclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BROADWELL-SSE-LABEL: test_aesenclast:
; BROADWELL-SSE: # %bb.0:
; BROADWELL-SSE-NEXT: aesenclast %xmm1, %xmm0 # sched: [7:1.00]
; BROADWELL-SSE-NEXT: aesenclast (%rdi), %xmm0 # sched: [12:1.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-LABEL: test_aesenclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
[X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU. Adding the scheduling information for the Browadwell (BDW) CPU target. This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target. We used the scheduling information retrieved from the Broadwell architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction. The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175. Performance fluctuations may be expected due to code alignment effects. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D39054 Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01 llvm-svn: 316492
2017-10-25 04:19:47 +08:00
; BROADWELL-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [12:1.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKYLAKE-SSE-LABEL: test_aesenclast:
; SKYLAKE-SSE: # %bb.0:
; SKYLAKE-SSE-NEXT: aesenclast %xmm1, %xmm0 # sched: [4:1.00]
; SKYLAKE-SSE-NEXT: aesenclast (%rdi), %xmm0 # sched: [10:1.00]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
; SKYLAKE-LABEL: test_aesenclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86][Skylake] Adding the scheduling information for the SkylakeClient target This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879. Please expect some performance fluctuations due to code alignment effects. Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena Differential Revision: https://reviews.llvm.org/D37294 llvm-svn: 313613
2017-09-19 14:19:27 +08:00
; SKYLAKE-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
[X86][SKL] Updated scheduling information for the SkylakeClient target Updated the scheduling information for the SkylakeClient target with the following changes: 1. regrouped the instructions after adding load and store latencies. 2. regrouped the instructions after adding identified missing ports in several groups. The changes were made after revisiting the latencies impact of all the load and store uOps. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D38727 Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f llvm-svn: 315978
2017-10-17 14:47:04 +08:00
; SKYLAKE-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKX-SSE-LABEL: test_aesenclast:
; SKX-SSE: # %bb.0:
; SKX-SSE-NEXT: aesenclast %xmm1, %xmm0 # sched: [4:1.00]
; SKX-SSE-NEXT: aesenclast (%rdi), %xmm0 # sched: [10:1.00]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_aesenclast:
; SKX: # %bb.0:
; SKX-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
; SKX-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
[NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler model Adding the baseline tests in a preparatory NFC commit, so that the actual commit shows the *diff*. Yes, i'm aware that a few of these codegen-based sched tests are testing wrong instructions, i will fix that afterwards. For https://reviews.llvm.org/D52779 llvm-svn: 345462
2018-10-28 04:36:11 +08:00
; BDVER2-SSE-LABEL: test_aesenclast:
; BDVER2-SSE: # %bb.0:
; BDVER2-SSE-NEXT: aesenclast %xmm1, %xmm0 # sched: [7:1.00]
; BDVER2-SSE-NEXT: aesenclast (%rdi), %xmm0 # sched: [13:1.00]
; BDVER2-SSE-NEXT: retq # sched: [1:1.00]
;
; BDVER2-LABEL: test_aesenclast:
; BDVER2: # %bb.0:
; BDVER2-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
; BDVER2-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
; BDVER2-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BTVER2-SSE-LABEL: test_aesenclast:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: aesenclast %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: aesenclast (%rdi), %xmm0 # sched: [8:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-LABEL: test_aesenclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; ZNVER1-SSE-LABEL: test_aesenclast:
; ZNVER1-SSE: # %bb.0:
; ZNVER1-SSE-NEXT: aesenclast %xmm1, %xmm0 # sched: [4:0.50]
; ZNVER1-SSE-NEXT: aesenclast (%rdi), %xmm0 # sched: [11:0.50]
; ZNVER1-SSE-NEXT: retq # sched: [1:0.50]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-LABEL: test_aesenclast:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [11:0.50]
AMD family 17h (znver1) scheduler model update. Summary: This patch enables the following: 1) Regex based Instruction itineraries for integer instructions. 2) The instructions are grouped as per the nature of the instructions (move, arithmetic, logic, Misc, Control Transfer). 3) FP instructions and their itineraries are added which includes values for SSE4A, BMI, BMI2 and SHA instructions. Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36617 llvm-svn: 312237
2017-08-31 20:38:35 +08:00
; ZNVER1-NEXT: retq # sched: [1:0.50]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
%1 = load <2 x i64>, <2 x i64> *%a2, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %a0, <2 x i64> %a1)
%3 = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %2, <2 x i64> %1)
ret <2 x i64> %3
}
declare <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64>, <2 x i64>)
define <2 x i64> @test_aesimc(<2 x i64> %a0, <2 x i64> *%a1) {
; GENERIC-LABEL: test_aesimc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; GENERIC-NEXT: aesimc %xmm0, %xmm1 # sched: [12:2.00]
; GENERIC-NEXT: aesimc (%rdi), %xmm0 # sched: [18:2.00]
; GENERIC-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SLM-LABEL: test_aesimc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SLM-NEXT: aesimc %xmm0, %xmm1 # sched: [8:5.00]
; SLM-NEXT: aesimc (%rdi), %xmm0 # sched: [8:5.00]
; SLM-NEXT: por %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SANDY-SSE-LABEL: test_aesimc:
; SANDY-SSE: # %bb.0:
; SANDY-SSE-NEXT: aesimc %xmm0, %xmm1 # sched: [12:2.00]
; SANDY-SSE-NEXT: aesimc (%rdi), %xmm0 # sched: [18:2.00]
; SANDY-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-LABEL: test_aesimc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-NEXT: vaesimc %xmm0, %xmm0 # sched: [12:2.00]
; SANDY-NEXT: vaesimc (%rdi), %xmm1 # sched: [18:2.00]
; SANDY-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; HASWELL-SSE-LABEL: test_aesimc:
; HASWELL-SSE: # %bb.0:
; HASWELL-SSE-NEXT: aesimc %xmm0, %xmm1 # sched: [14:2.00]
; HASWELL-SSE-NEXT: aesimc (%rdi), %xmm0 # sched: [20:2.00]
; HASWELL-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-LABEL: test_aesimc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-NEXT: vaesimc %xmm0, %xmm0 # sched: [14:2.00]
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: vaesimc (%rdi), %xmm1 # sched: [20:2.00]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: retq # sched: [7:1.00]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BROADWELL-SSE-LABEL: test_aesimc:
; BROADWELL-SSE: # %bb.0:
; BROADWELL-SSE-NEXT: aesimc (%rdi), %xmm1 # sched: [19:2.00]
; BROADWELL-SSE-NEXT: aesimc %xmm0, %xmm0 # sched: [14:2.00]
; BROADWELL-SSE-NEXT: por %xmm0, %xmm1 # sched: [1:0.33]
; BROADWELL-SSE-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.33]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-LABEL: test_aesimc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
Revert "[X86] Flag BroadWell scheduler model as complete" This reverts commit r320308. r320308 crashes LLC, please see the llvm-commits thread for a reproducer. llvm-svn: 320508
2017-12-13 02:40:58 +08:00
; BROADWELL-NEXT: vaesimc (%rdi), %xmm1 # sched: [19:2.00]
Reapply "[X86] Flag BroadWell scheduler model as complete" This reverts commit r320508, in effect re-applying r320308. Simon has already reverted the parts that caused the crash that motivated the revert in r320492. llvm-svn: 320512
2017-12-13 03:11:31 +08:00
; BROADWELL-NEXT: vaesimc %xmm0, %xmm0 # sched: [14:2.00]
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
[X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU. Adding the scheduling information for the Browadwell (BDW) CPU target. This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target. We used the scheduling information retrieved from the Broadwell architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction. The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175. Performance fluctuations may be expected due to code alignment effects. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D39054 Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01 llvm-svn: 316492
2017-10-25 04:19:47 +08:00
; BROADWELL-NEXT: retq # sched: [7:1.00]
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKYLAKE-SSE-LABEL: test_aesimc:
; SKYLAKE-SSE: # %bb.0:
; SKYLAKE-SSE-NEXT: aesimc %xmm0, %xmm1 # sched: [8:2.00]
; SKYLAKE-SSE-NEXT: aesimc (%rdi), %xmm0 # sched: [14:2.00]
; SKYLAKE-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
; SKYLAKE-LABEL: test_aesimc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86][Skylake] Adding the scheduling information for the SkylakeClient target This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879. Please expect some performance fluctuations due to code alignment effects. Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena Differential Revision: https://reviews.llvm.org/D37294 llvm-svn: 313613
2017-09-19 14:19:27 +08:00
; SKYLAKE-NEXT: vaesimc %xmm0, %xmm0 # sched: [8:2.00]
[X86][SKL] Updated scheduling information for the SkylakeClient target Updated the scheduling information for the SkylakeClient target with the following changes: 1. regrouped the instructions after adding load and store latencies. 2. regrouped the instructions after adding identified missing ports in several groups. The changes were made after revisiting the latencies impact of all the load and store uOps. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D38727 Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f llvm-svn: 315978
2017-10-17 14:47:04 +08:00
; SKYLAKE-NEXT: vaesimc (%rdi), %xmm1 # sched: [14:2.00]
; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKX-SSE-LABEL: test_aesimc:
; SKX-SSE: # %bb.0:
; SKX-SSE-NEXT: aesimc %xmm0, %xmm1 # sched: [8:2.00]
; SKX-SSE-NEXT: aesimc (%rdi), %xmm0 # sched: [14:2.00]
; SKX-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_aesimc:
; SKX: # %bb.0:
; SKX-NEXT: vaesimc %xmm0, %xmm0 # sched: [8:2.00]
; SKX-NEXT: vaesimc (%rdi), %xmm1 # sched: [14:2.00]
; SKX-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
[NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler model Adding the baseline tests in a preparatory NFC commit, so that the actual commit shows the *diff*. Yes, i'm aware that a few of these codegen-based sched tests are testing wrong instructions, i will fix that afterwards. For https://reviews.llvm.org/D52779 llvm-svn: 345462
2018-10-28 04:36:11 +08:00
; BDVER2-SSE-LABEL: test_aesimc:
; BDVER2-SSE: # %bb.0:
; BDVER2-SSE-NEXT: aesimc %xmm0, %xmm1 # sched: [12:2.00]
; BDVER2-SSE-NEXT: aesimc (%rdi), %xmm0 # sched: [18:2.00]
; BDVER2-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; BDVER2-SSE-NEXT: retq # sched: [1:1.00]
;
; BDVER2-LABEL: test_aesimc:
; BDVER2: # %bb.0:
; BDVER2-NEXT: vaesimc %xmm0, %xmm0 # sched: [12:2.00]
; BDVER2-NEXT: vaesimc (%rdi), %xmm1 # sched: [18:2.00]
; BDVER2-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; BDVER2-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BTVER2-SSE-LABEL: test_aesimc:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: aesimc %xmm0, %xmm1 # sched: [2:1.00]
; BTVER2-SSE-NEXT: aesimc (%rdi), %xmm0 # sched: [7:1.00]
; BTVER2-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.50]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-LABEL: test_aesimc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-NEXT: vaesimc (%rdi), %xmm1 # sched: [7:1.00]
; BTVER2-NEXT: vaesimc %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; ZNVER1-SSE-LABEL: test_aesimc:
; ZNVER1-SSE: # %bb.0:
; ZNVER1-SSE-NEXT: aesimc %xmm0, %xmm1 # sched: [4:0.50]
; ZNVER1-SSE-NEXT: aesimc (%rdi), %xmm0 # sched: [11:0.50]
; ZNVER1-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.25]
; ZNVER1-SSE-NEXT: retq # sched: [1:0.50]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-LABEL: test_aesimc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-NEXT: vaesimc (%rdi), %xmm1 # sched: [11:0.50]
; ZNVER1-NEXT: vaesimc %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
AMD family 17h (znver1) scheduler model update. Summary: This patch enables the following: 1) Regex based Instruction itineraries for integer instructions. 2) The instructions are grouped as per the nature of the instructions (move, arithmetic, logic, Misc, Control Transfer). 3) FP instructions and their itineraries are added which includes values for SSE4A, BMI, BMI2 and SHA instructions. Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36617 llvm-svn: 312237
2017-08-31 20:38:35 +08:00
; ZNVER1-NEXT: retq # sched: [1:0.50]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
%1 = load <2 x i64>, <2 x i64> *%a1, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %a0)
%3 = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %1)
%4 = or <2 x i64> %2, %3
ret <2 x i64> %4
}
declare <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64>)
define <2 x i64> @test_aeskeygenassist(<2 x i64> %a0, <2 x i64> *%a1) {
; GENERIC-LABEL: test_aeskeygenassist:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; GENERIC-NEXT: aeskeygenassist $7, %xmm0, %xmm1 # sched: [8:3.67]
; GENERIC-NEXT: aeskeygenassist $7, (%rdi), %xmm0 # sched: [8:3.33]
; GENERIC-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SLM-LABEL: test_aeskeygenassist:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SLM-NEXT: aeskeygenassist $7, %xmm0, %xmm1 # sched: [8:5.00]
; SLM-NEXT: aeskeygenassist $7, (%rdi), %xmm0 # sched: [8:5.00]
; SLM-NEXT: por %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SANDY-SSE-LABEL: test_aeskeygenassist:
; SANDY-SSE: # %bb.0:
; SANDY-SSE-NEXT: aeskeygenassist $7, %xmm0, %xmm1 # sched: [8:3.67]
; SANDY-SSE-NEXT: aeskeygenassist $7, (%rdi), %xmm0 # sched: [8:3.33]
; SANDY-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-LABEL: test_aeskeygenassist:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; SANDY-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [8:3.67]
; SANDY-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [8:3.33]
; SANDY-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; HASWELL-SSE-LABEL: test_aeskeygenassist:
; HASWELL-SSE: # %bb.0:
; HASWELL-SSE-NEXT: aeskeygenassist $7, %xmm0, %xmm1 # sched: [29:7.00]
; HASWELL-SSE-NEXT: aeskeygenassist $7, (%rdi), %xmm0 # sched: [34:7.00]
; HASWELL-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-LABEL: test_aeskeygenassist:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][Haswell] Updating HSW instruction scheduling information This patch completely replaces the instruction scheduling information for the Haswell architecture target by modifying the file X86SchedHaswell.td located under the X86 Target. We used the scheduling information retrieved from the Haswell architects in order to replace and modify the existing scheduling. The patch continues the scheduling replacement effort started with the SNB target in r307529 and r310792. Information includes latency, number of micro-Ops and used ports by each HSW instruction. Please expect some performance fluctuations due to code alignment effects. Reviewers: RKSimon, zvi, aymanmus, craig.topper, m_zuckerman, igorb, dim, chandlerc, aaboud Differential Revision: https://reviews.llvm.org/D36663 llvm-svn: 311879
2017-08-28 18:04:16 +08:00
; HASWELL-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [29:7.00]
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [34:7.00]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; HASWELL-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: retq # sched: [7:1.00]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BROADWELL-SSE-LABEL: test_aeskeygenassist:
; BROADWELL-SSE: # %bb.0:
; BROADWELL-SSE-NEXT: aeskeygenassist $7, %xmm0, %xmm1 # sched: [29:7.00]
; BROADWELL-SSE-NEXT: aeskeygenassist $7, (%rdi), %xmm0 # sched: [33:7.00]
; BROADWELL-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-LABEL: test_aeskeygenassist:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [29:7.00]
[X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU. Adding the scheduling information for the Browadwell (BDW) CPU target. This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target. We used the scheduling information retrieved from the Broadwell architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction. The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175. Performance fluctuations may be expected due to code alignment effects. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D39054 Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01 llvm-svn: 316492
2017-10-25 04:19:47 +08:00
; BROADWELL-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [33:7.00]
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
; BROADWELL-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
[X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU. Adding the scheduling information for the Browadwell (BDW) CPU target. This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target. We used the scheduling information retrieved from the Broadwell architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction. The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175. Performance fluctuations may be expected due to code alignment effects. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D39054 Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01 llvm-svn: 316492
2017-10-25 04:19:47 +08:00
; BROADWELL-NEXT: retq # sched: [7:1.00]
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
2017-10-17 21:45:39 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKYLAKE-SSE-LABEL: test_aeskeygenassist:
; SKYLAKE-SSE: # %bb.0:
; SKYLAKE-SSE-NEXT: aeskeygenassist $7, %xmm0, %xmm1 # sched: [20:6.00]
; SKYLAKE-SSE-NEXT: aeskeygenassist $7, (%rdi), %xmm0 # sched: [25:6.00]
; SKYLAKE-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
; SKYLAKE-LABEL: test_aeskeygenassist:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86][Skylake] Adding the scheduling information for the SkylakeClient target This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879. Please expect some performance fluctuations due to code alignment effects. Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena Differential Revision: https://reviews.llvm.org/D37294 llvm-svn: 313613
2017-09-19 14:19:27 +08:00
; SKYLAKE-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [20:6.00]
[X86][SKL] Updated scheduling information for the SkylakeClient target Updated the scheduling information for the SkylakeClient target with the following changes: 1. regrouped the instructions after adding load and store latencies. 2. regrouped the instructions after adding identified missing ports in several groups. The changes were made after revisiting the latencies impact of all the load and store uOps. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D38727 Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f llvm-svn: 315978
2017-10-17 14:47:04 +08:00
; SKYLAKE-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [25:6.00]
; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regression tests NFC. Replaced duplicated HASWELL prefixes in run commands in the X86 Code Gen regression tests by the SKYLAKE prefix when the -mcpu is set to skylake. The fix is needed in preparation of an upcoming patch containing the Skylake scheduling info. Reviewers: zvi, RKSimon, aymanmus, igorb Differential Revision: https://reviews.llvm.org/D37258 llvm-svn: 312103
2017-08-30 16:08:50 +08:00
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; SKX-SSE-LABEL: test_aeskeygenassist:
; SKX-SSE: # %bb.0:
; SKX-SSE-NEXT: aeskeygenassist $7, %xmm0, %xmm1 # sched: [20:6.00]
; SKX-SSE-NEXT: aeskeygenassist $7, (%rdi), %xmm0 # sched: [25:6.00]
; SKX-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_aeskeygenassist:
; SKX: # %bb.0:
; SKX-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [20:6.00]
; SKX-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [25:6.00]
; SKX-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
[NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler model Adding the baseline tests in a preparatory NFC commit, so that the actual commit shows the *diff*. Yes, i'm aware that a few of these codegen-based sched tests are testing wrong instructions, i will fix that afterwards. For https://reviews.llvm.org/D52779 llvm-svn: 345462
2018-10-28 04:36:11 +08:00
; BDVER2-SSE-LABEL: test_aeskeygenassist:
; BDVER2-SSE: # %bb.0:
; BDVER2-SSE-NEXT: aeskeygenassist $7, %xmm0, %xmm1 # sched: [8:3.67]
; BDVER2-SSE-NEXT: aeskeygenassist $7, (%rdi), %xmm0 # sched: [8:3.33]
; BDVER2-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.33]
; BDVER2-SSE-NEXT: retq # sched: [1:1.00]
;
; BDVER2-LABEL: test_aeskeygenassist:
; BDVER2: # %bb.0:
; BDVER2-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [8:3.67]
; BDVER2-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [8:3.33]
; BDVER2-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; BDVER2-NEXT: retq # sched: [1:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; BTVER2-SSE-LABEL: test_aeskeygenassist:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: aeskeygenassist $7, %xmm0, %xmm1 # sched: [2:1.00]
; BTVER2-SSE-NEXT: aeskeygenassist $7, (%rdi), %xmm0 # sched: [7:1.00]
; BTVER2-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.50]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-LABEL: test_aeskeygenassist:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; BTVER2-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [7:1.00]
; BTVER2-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
2018-03-24 23:05:12 +08:00
; ZNVER1-SSE-LABEL: test_aeskeygenassist:
; ZNVER1-SSE: # %bb.0:
; ZNVER1-SSE-NEXT: aeskeygenassist $7, %xmm0, %xmm1 # sched: [4:0.50]
; ZNVER1-SSE-NEXT: aeskeygenassist $7, (%rdi), %xmm0 # sched: [11:0.50]
; ZNVER1-SSE-NEXT: por %xmm1, %xmm0 # sched: [1:0.25]
; ZNVER1-SSE-NEXT: retq # sched: [1:0.50]
;
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-LABEL: test_aeskeygenassist:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
; ZNVER1-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [11:0.50]
; ZNVER1-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
AMD family 17h (znver1) scheduler model update. Summary: This patch enables the following: 1) Regex based Instruction itineraries for integer instructions. 2) The instructions are grouped as per the nature of the instructions (move, arithmetic, logic, Misc, Control Transfer). 3) FP instructions and their itineraries are added which includes values for SSE4A, BMI, BMI2 and SHA instructions. Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36617 llvm-svn: 312237
2017-08-31 20:38:35 +08:00
; ZNVER1-NEXT: retq # sched: [1:0.50]
[X86][AES] Add scheduling latency/throughput tests for AES instructions llvm-svn: 311167
2017-08-18 23:26:51 +08:00
%1 = load <2 x i64>, <2 x i64> *%a1, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %a0, i8 7)
%3 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %1, i8 7)
%4 = or <2 x i64> %2, %3
ret <2 x i64> %4
}
declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8)