2018-04-10 16:16:37 +08:00
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//===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the available hardware counters for various subtargets.
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//
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//===----------------------------------------------------------------------===//
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2018-10-25 15:44:01 +08:00
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def UnhaltedCoreCyclesPfmCounter : PfmCounter<"unhalted_core_cycles">;
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def UopsIssuedPfmCounter : PfmCounter<"uops_issued:any">;
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def SandyBridgePfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"SBPort0", "uops_dispatched_port:port_0">,
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PfmIssueCounter<"SBPort1", "uops_dispatched_port:port_1">,
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PfmIssueCounter<"SBPort23", "uops_dispatched_port:port_2 + uops_dispatched_port:port_3">,
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PfmIssueCounter<"SBPort4", "uops_dispatched_port:port_4">,
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PfmIssueCounter<"SBPort5", "uops_dispatched_port:port_5">
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];
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2018-04-10 16:16:37 +08:00
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}
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2018-10-25 15:44:01 +08:00
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def : PfmCountersBinding<"sandybridge", SandyBridgePfmCounters>;
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2018-04-10 16:16:37 +08:00
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2018-10-25 15:44:01 +08:00
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def HaswellPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"HWPort0", "uops_dispatched_port:port_0">,
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PfmIssueCounter<"HWPort1", "uops_dispatched_port:port_1">,
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PfmIssueCounter<"HWPort2", "uops_dispatched_port:port_2">,
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PfmIssueCounter<"HWPort3", "uops_dispatched_port:port_3">,
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PfmIssueCounter<"HWPort4", "uops_dispatched_port:port_4">,
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PfmIssueCounter<"HWPort5", "uops_dispatched_port:port_5">,
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PfmIssueCounter<"HWPort6", "uops_dispatched_port:port_6">,
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PfmIssueCounter<"HWPort7", "uops_dispatched_port:port_7">
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];
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2018-04-10 16:16:37 +08:00
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}
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2018-10-25 15:44:01 +08:00
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def : PfmCountersBinding<"haswell", HaswellPfmCounters>;
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2018-04-10 16:16:37 +08:00
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2018-10-25 15:44:01 +08:00
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def BroadwellPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"BWPort0", "uops_executed_port:port_0">,
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PfmIssueCounter<"BWPort1", "uops_executed_port:port_1">,
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PfmIssueCounter<"BWPort2", "uops_executed_port:port_2">,
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PfmIssueCounter<"BWPort3", "uops_executed_port:port_3">,
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PfmIssueCounter<"BWPort4", "uops_executed_port:port_4">,
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PfmIssueCounter<"BWPort5", "uops_executed_port:port_5">,
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PfmIssueCounter<"BWPort6", "uops_executed_port:port_6">,
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PfmIssueCounter<"BWPort7", "uops_executed_port:port_7">
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];
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2018-04-10 16:16:37 +08:00
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}
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2018-10-25 15:44:01 +08:00
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def : PfmCountersBinding<"broadwell", BroadwellPfmCounters>;
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2018-04-10 16:16:37 +08:00
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2018-10-25 15:44:01 +08:00
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def SkylakeClientPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"SKLPort0", "uops_dispatched_port:port_0">,
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PfmIssueCounter<"SKLPort1", "uops_dispatched_port:port_1">,
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PfmIssueCounter<"SKLPort2", "uops_dispatched_port:port_2">,
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PfmIssueCounter<"SKLPort3", "uops_dispatched_port:port_3">,
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PfmIssueCounter<"SKLPort4", "uops_dispatched_port:port_4">,
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PfmIssueCounter<"SKLPort5", "uops_dispatched_port:port_5">,
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PfmIssueCounter<"SKLPort6", "uops_dispatched_port:port_6">,
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PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7">
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];
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2018-04-10 16:16:37 +08:00
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}
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2018-10-25 15:44:01 +08:00
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def : PfmCountersBinding<"skylake", SkylakeClientPfmCounters>;
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2018-04-10 16:16:37 +08:00
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2018-10-25 15:44:01 +08:00
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def SkylakeServerPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"SKXPort0", "uops_dispatched_port:port_0">,
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PfmIssueCounter<"SKXPort1", "uops_dispatched_port:port_1">,
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PfmIssueCounter<"SKXPort2", "uops_dispatched_port:port_2">,
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PfmIssueCounter<"SKXPort3", "uops_dispatched_port:port_3">,
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PfmIssueCounter<"SKXPort4", "uops_dispatched_port:port_4">,
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PfmIssueCounter<"SKXPort5", "uops_dispatched_port:port_5">,
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PfmIssueCounter<"SKXPort6", "uops_dispatched_port:port_6">,
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PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7">
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];
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2018-04-10 16:16:37 +08:00
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}
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2018-10-25 15:44:01 +08:00
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def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>;
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2018-05-24 22:54:32 +08:00
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2018-10-25 15:44:01 +08:00
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def BtVer2PfmCounters : ProcPfmCounters {
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let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
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let UopsCounter = PfmCounter<"retired_uops">;
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let IssueCounters = [
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PfmIssueCounter<"JFPU0", "dispatched_fpu:pipe0">,
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PfmIssueCounter<"JFPU1", "dispatched_fpu:pipe1">
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];
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2018-05-24 22:54:32 +08:00
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}
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2018-10-25 15:44:01 +08:00
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def : PfmCountersBinding<"btver2", BtVer2PfmCounters>;
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