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llvm-project/llvm/test/CodeGen/X86/inlineasm-sched-bug.ll

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This patch addresses a problem with the Post RA scheduler generating an incorrect instruction sequence due to it not being aware that an inline assembly instruction may reference memory. This patch fixes the problem by causing the scheduler to always assume that any inline assembly code instruction could access memory. This is necessary because the internal representation of the inline instruction does not include any information about memory accesses. This should fix PR13504. llvm-svn: 166929
2012-10-29 23:01:23 +08:00
; PR13504
[X86][NFC] Replace "<%s" with "< %s" in run-lines. While i have no intention of actually commiting regeneration of the check lines in these test files with update_llc_test_checks, lack of that whitespace breaks that util, which is mildly inconvenient. llvm-svn: 352318
2019-01-27 23:36:35 +08:00
; RUN: llc -mtriple=i686-- -mcpu=atom < %s | FileCheck %s
This patch addresses a problem with the Post RA scheduler generating an incorrect instruction sequence due to it not being aware that an inline assembly instruction may reference memory. This patch fixes the problem by causing the scheduler to always assume that any inline assembly code instruction could access memory. This is necessary because the internal representation of the inline instruction does not include any information about memory accesses. This should fix PR13504. llvm-svn: 166929
2012-10-29 23:01:23 +08:00
; CHECK: bsfl
; CHECK-NOT: movl
define i32 @foo(i32 %treemap) nounwind uwtable {
entry:
%sub = sub i32 0, %treemap
%and = and i32 %treemap, %sub
%0 = tail call i32 asm "bsfl $1,$0\0A\09", "=r,rm,~{dirflag},~{fpsr},~{flags}"(i32 %and) nounwind
ret i32 %0
}