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llvm-project/llvm/test/CodeGen/X86/avx2-conversions.ll

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Make utils/update_llc_test_checks.py note that the assertions are autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
2015-11-24 05:33:58 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s --check-prefix=X64
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
define <4 x i32> @trunc4(<4 x i64> %A) nounwind {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: trunc4:
; X32: ## BB#0:
; X32-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X32-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: trunc4:
; X64: ## BB#0:
; X64-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X64-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
%B = trunc <4 x i64> %A to <4 x i32>
ret <4 x i32>%B
}
define <8 x i16> @trunc8(<8 x i32> %A) nounwind {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: trunc8:
; X32: ## BB#0:
[X86] In LowerTRUNCATE, create an ISD::VECTOR_SHUFFLE instead of explicitly creating a PSHUFB. This will be lowered by regular shuffle lowering to a PSHUFB later. Similar was already done for several other shuffles in this function. The test changes are because the old code used explicity zeroing for elements that could have been undef. While I was here I also changed other shuffle vectors in the same function to use the same input twice instead of creating UNDEF nodes. getVectorShuffle can create the UNDEF for us. llvm-svn: 294130
2017-02-06 02:33:14 +08:00
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X32-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: trunc8:
; X64: ## BB#0:
[X86] In LowerTRUNCATE, create an ISD::VECTOR_SHUFFLE instead of explicitly creating a PSHUFB. This will be lowered by regular shuffle lowering to a PSHUFB later. Similar was already done for several other shuffles in this function. The test changes are because the old code used explicity zeroing for elements that could have been undef. While I was here I also changed other shuffle vectors in the same function to use the same input twice instead of creating UNDEF nodes. getVectorShuffle can create the UNDEF for us. llvm-svn: 294130
2017-02-06 02:33:14 +08:00
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X64-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; X64-NEXT: vzeroupper
; X64-NEXT: retq
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
%B = trunc <8 x i32> %A to <8 x i16>
ret <8 x i16>%B
}
define <4 x i64> @sext4(<4 x i32> %A) nounwind {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: sext4:
; X32: ## BB#0:
; X32-NEXT: vpmovsxdq %xmm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: sext4:
; X64: ## BB#0:
; X64-NEXT: vpmovsxdq %xmm0, %ymm0
; X64-NEXT: retq
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
%B = sext <4 x i32> %A to <4 x i64>
ret <4 x i64>%B
}
define <8 x i32> @sext8(<8 x i16> %A) nounwind {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: sext8:
; X32: ## BB#0:
; X32-NEXT: vpmovsxwd %xmm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: sext8:
; X64: ## BB#0:
; X64-NEXT: vpmovsxwd %xmm0, %ymm0
; X64-NEXT: retq
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
%B = sext <8 x i16> %A to <8 x i32>
ret <8 x i32>%B
}
define <4 x i64> @zext4(<4 x i32> %A) nounwind {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: zext4:
; X32: ## BB#0:
; X32-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; X32-NEXT: retl
;
; X64-LABEL: zext4:
; X64: ## BB#0:
; X64-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; X64-NEXT: retq
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
%B = zext <4 x i32> %A to <4 x i64>
ret <4 x i64>%B
}
define <8 x i32> @zext8(<8 x i16> %A) nounwind {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: zext8:
; X32: ## BB#0:
; X32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; X32-NEXT: retl
;
; X64-LABEL: zext8:
; X64: ## BB#0:
; X64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; X64-NEXT: retq
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
%B = zext <8 x i16> %A to <8 x i32>
ret <8 x i32>%B
}
[X86][AVX2] Refreshed avx2 conversion tests llvm-svn: 243248
2015-07-27 01:01:16 +08:00
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
define <8 x i32> @zext_8i8_8i32(<8 x i8> %A) nounwind {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: zext_8i8_8i32:
; X32: ## BB#0:
; X32-NEXT: vpand LCPI6_0, %xmm0, %xmm0
; X32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; X32-NEXT: retl
;
; X64-LABEL: zext_8i8_8i32:
; X64: ## BB#0:
; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; X64-NEXT: retq
[X86][AVX2] Refreshed avx2 conversion tests llvm-svn: 243248
2015-07-27 01:01:16 +08:00
%B = zext <8 x i8> %A to <8 x i32>
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
ret <8 x i32>%B
}
X86: Custom lower zext v16i8 to v16i16. On sandy bridge (PR17654) we now get vpxor %xmm1, %xmm1, %xmm1 vpunpckhbw %xmm1, %xmm0, %xmm2 vpunpcklbw %xmm1, %xmm0, %xmm0 vinsertf128 $1, %xmm2, %ymm0, %ymm0 On haswell it's a simple vpmovzxbw %xmm0, %ymm0 There is a maze of duplicated and dead transforms and patterns in this area. Remove the dead custom lowering of zext v8i16 to v8i32, that's already handled by LowerAVXExtend. llvm-svn: 193262
2013-10-24 03:19:04 +08:00
define <16 x i16> @zext_16i8_16i16(<16 x i8> %z) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: zext_16i8_16i16:
; X32: ## BB#0:
; X32-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; X32-NEXT: retl
;
; X64-LABEL: zext_16i8_16i16:
; X64: ## BB#0:
; X64-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; X64-NEXT: retq
X86: Custom lower zext v16i8 to v16i16. On sandy bridge (PR17654) we now get vpxor %xmm1, %xmm1, %xmm1 vpunpckhbw %xmm1, %xmm0, %xmm2 vpunpcklbw %xmm1, %xmm0, %xmm0 vinsertf128 $1, %xmm2, %ymm0, %ymm0 On haswell it's a simple vpmovzxbw %xmm0, %ymm0 There is a maze of duplicated and dead transforms and patterns in this area. Remove the dead custom lowering of zext v8i16 to v8i32, that's already handled by LowerAVXExtend. llvm-svn: 193262
2013-10-24 03:19:04 +08:00
%t = zext <16 x i8> %z to <16 x i16>
ret <16 x i16> %t
}
X86: Custom lower sext v16i8 to v16i16, and the corresponding truncate. Also update the cost model. llvm-svn: 193270
2013-10-24 05:06:07 +08:00
define <16 x i16> @sext_16i8_16i16(<16 x i8> %z) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: sext_16i8_16i16:
; X32: ## BB#0:
; X32-NEXT: vpmovsxbw %xmm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: sext_16i8_16i16:
; X64: ## BB#0:
; X64-NEXT: vpmovsxbw %xmm0, %ymm0
; X64-NEXT: retq
X86: Custom lower sext v16i8 to v16i16, and the corresponding truncate. Also update the cost model. llvm-svn: 193270
2013-10-24 05:06:07 +08:00
%t = sext <16 x i8> %z to <16 x i16>
ret <16 x i16> %t
}
define <16 x i8> @trunc_16i16_16i8(<16 x i16> %z) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: trunc_16i16_16i8:
; X32: ## BB#0:
; X32-NEXT: vextracti128 $1, %ymm0, %xmm1
; X32-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
; X32-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; X32-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; X32-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: trunc_16i16_16i8:
; X64: ## BB#0:
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
; X64-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; X64-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; X64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X64-NEXT: vzeroupper
; X64-NEXT: retq
X86: Custom lower sext v16i8 to v16i16, and the corresponding truncate. Also update the cost model. llvm-svn: 193270
2013-10-24 05:06:07 +08:00
%t = trunc <16 x i16> %z to <16 x i8>
ret <16 x i8> %t
}
Optimized load + SIGN_EXTEND patterns in the X86 backend. llvm-svn: 170506
2012-12-19 15:50:20 +08:00
define <4 x i64> @load_sext_test1(<4 x i32> *%ptr) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: load_sext_test1:
; X32: ## BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpmovsxdq (%eax), %ymm0
; X32-NEXT: retl
;
; X64-LABEL: load_sext_test1:
; X64: ## BB#0:
; X64-NEXT: vpmovsxdq (%rdi), %ymm0
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%X = load <4 x i32>, <4 x i32>* %ptr
Optimized load + SIGN_EXTEND patterns in the X86 backend. llvm-svn: 170506
2012-12-19 15:50:20 +08:00
%Y = sext <4 x i32> %X to <4 x i64>
ret <4 x i64>%Y
}
define <4 x i64> @load_sext_test2(<4 x i8> *%ptr) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: load_sext_test2:
; X32: ## BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpmovsxbq (%eax), %ymm0
; X32-NEXT: retl
;
; X64-LABEL: load_sext_test2:
; X64: ## BB#0:
; X64-NEXT: vpmovsxbq (%rdi), %ymm0
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%X = load <4 x i8>, <4 x i8>* %ptr
Optimized load + SIGN_EXTEND patterns in the X86 backend. llvm-svn: 170506
2012-12-19 15:50:20 +08:00
%Y = sext <4 x i8> %X to <4 x i64>
ret <4 x i64>%Y
}
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
Optimized load + SIGN_EXTEND patterns in the X86 backend. llvm-svn: 170506
2012-12-19 15:50:20 +08:00
define <4 x i64> @load_sext_test3(<4 x i16> *%ptr) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: load_sext_test3:
; X32: ## BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpmovsxwq (%eax), %ymm0
; X32-NEXT: retl
;
; X64-LABEL: load_sext_test3:
; X64: ## BB#0:
; X64-NEXT: vpmovsxwq (%rdi), %ymm0
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%X = load <4 x i16>, <4 x i16>* %ptr
Optimized load + SIGN_EXTEND patterns in the X86 backend. llvm-svn: 170506
2012-12-19 15:50:20 +08:00
%Y = sext <4 x i16> %X to <4 x i64>
ret <4 x i64>%Y
}
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
Optimized load + SIGN_EXTEND patterns in the X86 backend. llvm-svn: 170506
2012-12-19 15:50:20 +08:00
define <8 x i32> @load_sext_test4(<8 x i16> *%ptr) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: load_sext_test4:
; X32: ## BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpmovsxwd (%eax), %ymm0
; X32-NEXT: retl
;
; X64-LABEL: load_sext_test4:
; X64: ## BB#0:
; X64-NEXT: vpmovsxwd (%rdi), %ymm0
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%X = load <8 x i16>, <8 x i16>* %ptr
Optimized load + SIGN_EXTEND patterns in the X86 backend. llvm-svn: 170506
2012-12-19 15:50:20 +08:00
%Y = sext <8 x i16> %X to <8 x i32>
ret <8 x i32>%Y
}
cleaned line endings in the newly added test file llvm-svn: 155315
2012-04-22 21:22:48 +08:00
Optimized load + SIGN_EXTEND patterns in the X86 backend. llvm-svn: 170506
2012-12-19 15:50:20 +08:00
define <8 x i32> @load_sext_test5(<8 x i8> *%ptr) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: load_sext_test5:
; X32: ## BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpmovsxbd (%eax), %ymm0
; X32-NEXT: retl
;
; X64-LABEL: load_sext_test5:
; X64: ## BB#0:
; X64-NEXT: vpmovsxbd (%rdi), %ymm0
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%X = load <8 x i8>, <8 x i8>* %ptr
Optimized load + SIGN_EXTEND patterns in the X86 backend. llvm-svn: 170506
2012-12-19 15:50:20 +08:00
%Y = sext <8 x i8> %X to <8 x i32>
ret <8 x i32>%Y
}