llvm-project/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir

# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
# TODO: add tests for additional configuration after the legalization supported
--- |
  define void @test_sub_v32i8() {
    %ret = sub <32 x i8> undef, undef
    ret void
  }

  define void @test_sub_v16i16() {
    %ret = sub <16 x i16> undef, undef
    ret void
  }

  define void @test_sub_v8i32() {
    %ret = sub <8 x i32> undef, undef
    ret void
  }

  define void @test_sub_v4i64() {
    %ret = sub <4 x i64> undef, undef
    ret void
  }

...
---
name:            test_sub_v32i8
# ALL-LABEL: name:  test_sub_v32i8
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
# AVX2:          %0(<32 x s8>) = IMPLICIT_DEF
# AVX2-NEXT:     %1(<32 x s8>) = IMPLICIT_DEF
# AVX2-NEXT:     %2(<32 x s8>) = G_SUB %0, %1
# AVX2-NEXT:     RET 0
body:             |
  bb.1 (%ir-block.0):
    liveins: %ymm0, %ymm1

    %0(<32 x s8>) = IMPLICIT_DEF
    %1(<32 x s8>) = IMPLICIT_DEF
    %2(<32 x s8>) = G_SUB %0, %1
    RET 0

...
---
name:            test_sub_v16i16
# ALL-LABEL: name:  test_sub_v16i16
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
# AVX2:          %0(<16 x s16>) = IMPLICIT_DEF
# AVX2-NEXT:     %1(<16 x s16>) = IMPLICIT_DEF
# AVX2-NEXT:     %2(<16 x s16>) = G_SUB %0, %1
# AVX2-NEXT:     RET 0
body:             |
  bb.1 (%ir-block.0):
    liveins: %ymm0, %ymm1

    %0(<16 x s16>) = IMPLICIT_DEF
    %1(<16 x s16>) = IMPLICIT_DEF
    %2(<16 x s16>) = G_SUB %0, %1
    RET 0

...
---
name:            test_sub_v8i32
# ALL-LABEL: name:  test_sub_v8i32
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
# AVX2:          %0(<8 x s32>) = IMPLICIT_DEF
# AVX2-NEXT:     %1(<8 x s32>) = IMPLICIT_DEF
# AVX2-NEXT:     %2(<8 x s32>) = G_SUB %0, %1
# AVX2-NEXT:     RET 0
body:             |
  bb.1 (%ir-block.0):
    liveins: %ymm0, %ymm1

    %0(<8 x s32>) = IMPLICIT_DEF
    %1(<8 x s32>) = IMPLICIT_DEF
    %2(<8 x s32>) = G_SUB %0, %1
    RET 0

...
---
name:            test_sub_v4i64
# ALL-LABEL: name:  test_sub_v4i64
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
# AVX2:          %0(<4 x s64>) = IMPLICIT_DEF
# AVX2-NEXT:     %1(<4 x s64>) = IMPLICIT_DEF
# AVX2-NEXT:     %2(<4 x s64>) = G_SUB %0, %1
# AVX2-NEXT:     RET 0
body:             |
  bb.1 (%ir-block.0):
    liveins: %ymm0, %ymm1

    %0(<4 x s64>) = IMPLICIT_DEF
    %1(<4 x s64>) = IMPLICIT_DEF
    %2(<4 x s64>) = G_SUB %0, %1
    RET 0

...