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llvm-project/llvm/test/CodeGen/ARM/arm32-rounding.ll

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[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; RUN: llc < %s -mtriple=armv8-linux-gnueabihf -mattr=+fp-armv8 | FileCheck --check-prefix=CHECK --check-prefix=DP %s
; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabihf -mattr=+fp-armv8,+d16,+fp-only-sp | FileCheck --check-prefix=SP %s
; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabihf -mattr=+fp-armv8,+d16 | FileCheck --check-prefix=DP %s
[AArch32] Add support for FP rounding operations for ARMv8/AArch32. Phabricator Revision: http://reviews.llvm.org/D4935 llvm-svn: 215772
2014-08-16 05:38:16 +08:00
; CHECK-LABEL: test1
; CHECK: vrintm.f32
define float @test1(float %a) {
entry:
%call = call float @floorf(float %a) nounwind readnone
ret float %call
}
; CHECK-LABEL: test2
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; SP: b floor
; DP: vrintm.f64
[AArch32] Add support for FP rounding operations for ARMv8/AArch32. Phabricator Revision: http://reviews.llvm.org/D4935 llvm-svn: 215772
2014-08-16 05:38:16 +08:00
define double @test2(double %a) {
entry:
%call = call double @floor(double %a) nounwind readnone
ret double %call
}
; CHECK-LABEL: test3
; CHECK: vrintp.f32
define float @test3(float %a) {
entry:
%call = call float @ceilf(float %a) nounwind readnone
ret float %call
}
; CHECK-LABEL: test4
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; SP: b ceil
; DP: vrintp.f64
[AArch32] Add support for FP rounding operations for ARMv8/AArch32. Phabricator Revision: http://reviews.llvm.org/D4935 llvm-svn: 215772
2014-08-16 05:38:16 +08:00
define double @test4(double %a) {
entry:
%call = call double @ceil(double %a) nounwind readnone
ret double %call
}
; CHECK-LABEL: test5
; CHECK: vrinta.f32
define float @test5(float %a) {
entry:
%call = call float @roundf(float %a) nounwind readnone
ret float %call
}
; CHECK-LABEL: test6
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; SP: b round
; DP: vrinta.f64
[AArch32] Add support for FP rounding operations for ARMv8/AArch32. Phabricator Revision: http://reviews.llvm.org/D4935 llvm-svn: 215772
2014-08-16 05:38:16 +08:00
define double @test6(double %a) {
entry:
%call = call double @round(double %a) nounwind readnone
ret double %call
}
; CHECK-LABEL: test7
; CHECK: vrintz.f32
define float @test7(float %a) {
entry:
%call = call float @truncf(float %a) nounwind readnone
ret float %call
}
; CHECK-LABEL: test8
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; SP: b trunc
; DP: vrintz.f64
[AArch32] Add support for FP rounding operations for ARMv8/AArch32. Phabricator Revision: http://reviews.llvm.org/D4935 llvm-svn: 215772
2014-08-16 05:38:16 +08:00
define double @test8(double %a) {
entry:
%call = call double @trunc(double %a) nounwind readnone
ret double %call
}
; CHECK-LABEL: test9
; CHECK: vrintr.f32
define float @test9(float %a) {
entry:
%call = call float @nearbyintf(float %a) nounwind readnone
ret float %call
}
; CHECK-LABEL: test10
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; SP: b nearbyint
; DP: vrintr.f64
[AArch32] Add support for FP rounding operations for ARMv8/AArch32. Phabricator Revision: http://reviews.llvm.org/D4935 llvm-svn: 215772
2014-08-16 05:38:16 +08:00
define double @test10(double %a) {
entry:
%call = call double @nearbyint(double %a) nounwind readnone
ret double %call
}
; CHECK-LABEL: test11
; CHECK: vrintx.f32
define float @test11(float %a) {
entry:
%call = call float @rintf(float %a) nounwind readnone
ret float %call
}
; CHECK-LABEL: test12
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; SP: b rint
; DP: vrintx.f64
[AArch32] Add support for FP rounding operations for ARMv8/AArch32. Phabricator Revision: http://reviews.llvm.org/D4935 llvm-svn: 215772
2014-08-16 05:38:16 +08:00
define double @test12(double %a) {
entry:
%call = call double @rint(double %a) nounwind readnone
ret double %call
}
declare float @floorf(float) nounwind readnone
declare double @floor(double) nounwind readnone
declare float @ceilf(float) nounwind readnone
declare double @ceil(double) nounwind readnone
declare float @roundf(float) nounwind readnone
declare double @round(double) nounwind readnone
declare float @truncf(float) nounwind readnone
declare double @trunc(double) nounwind readnone
declare float @nearbyintf(float) nounwind readnone
declare double @nearbyint(double) nounwind readnone
declare float @rintf(float) nounwind readnone
declare double @rint(double) nounwind readnone