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llvm-project/llvm/test/CodeGen/AArch64/arm64-big-stack.ll

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ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; RUN: llc < %s | FileCheck %s
target triple = "arm64-apple-macosx10"
; Check that big stacks are generated correctly.
; Currently, this is done by a sequence of sub instructions,
; which can encode immediate with a 12 bits mask an optionally
; shift left (up to 12). I.e., 16773120 is the biggest value.
; <rdar://12513931>
; CHECK-LABEL: foo:
ARM64: print canonical syntax for add/sub (imm) instructions. Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. llvm-svn: 207633
2014-04-30 19:19:15 +08:00
; CHECK: sub sp, sp, #4095, lsl #12
; CHECK: sub sp, sp, #4095, lsl #12
; CHECK: sub sp, sp, #2, lsl #12
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
define void @foo() nounwind ssp {
entry:
%buffer = alloca [33554432 x i8], align 1
%arraydecay = getelementptr inbounds [33554432 x i8]* %buffer, i64 0, i64 0
call void @doit(i8* %arraydecay) nounwind
ret void
}
declare void @doit(i8*)