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llvm-project/llvm/test/CodeGen/X86/2009-08-19-LoadNarrowingMis...

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Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81290
2009-09-09 07:54:48 +08:00
; RUN: llc < %s -march=x86 -mtriple=i386-pc-linux | FileCheck %s
PR4737: Fix a nasty bug in load narrowing with non-power-of-two types. llvm-svn: 79415
2009-08-19 16:46:10 +08:00
@a = external global i96, align 4
@b = external global i64, align 8
define void @c() nounwind {
; CHECK: movl a+8, %eax
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%srcval1 = load i96, i96* @a, align 4
PR4737: Fix a nasty bug in load narrowing with non-power-of-two types. llvm-svn: 79415
2009-08-19 16:46:10 +08:00
%sroa.store.elt2 = lshr i96 %srcval1, 64
%tmp = trunc i96 %sroa.store.elt2 to i64
; CHECK: movl %eax, b
; CHECK: movl $0, b+4
store i64 %tmp, i64* @b, align 8
ret void
}