2014-05-24 20:50:23 +08:00
|
|
|
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -fp-contract=fast | FileCheck %s
|
2014-04-15 22:00:06 +08:00
|
|
|
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s -check-prefix=CHECK-NOFAST
|
2013-01-31 20:12:40 +08:00
|
|
|
|
|
|
|
|
declare float @llvm.fma.f32(float, float, float)
|
|
|
|
|
declare double @llvm.fma.f64(double, double, double)
|
|
|
|
|
|
|
|
|
|
define float @test_fmadd(float %a, float %b, float %c) {
|
2013-07-12 22:54:12 +08:00
|
|
|
; CHECK-LABEL: test_fmadd:
|
|
|
|
|
; CHECK-NOFAST-LABEL: test_fmadd:
|
2013-01-31 20:12:40 +08:00
|
|
|
%val = call float @llvm.fma.f32(float %a, float %b, float %c)
|
|
|
|
|
; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
2013-01-31 20:12:40 +08:00
|
|
|
ret float %val
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define float @test_fmsub(float %a, float %b, float %c) {
|
2013-07-12 22:54:12 +08:00
|
|
|
; CHECK-LABEL: test_fmsub:
|
|
|
|
|
; CHECK-NOFAST-LABEL: test_fmsub:
|
2013-01-31 20:12:40 +08:00
|
|
|
%nega = fsub float -0.0, %a
|
|
|
|
|
%val = call float @llvm.fma.f32(float %nega, float %b, float %c)
|
|
|
|
|
; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
2013-01-31 20:12:40 +08:00
|
|
|
ret float %val
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define float @test_fnmadd(float %a, float %b, float %c) {
|
2013-07-12 22:54:12 +08:00
|
|
|
; CHECK-LABEL: test_fnmadd:
|
|
|
|
|
; CHECK-NOFAST-LABEL: test_fnmadd:
|
2013-12-24 08:40:10 +08:00
|
|
|
%nega = fsub float -0.0, %a
|
2013-01-31 20:12:40 +08:00
|
|
|
%negc = fsub float -0.0, %c
|
2013-12-24 08:40:10 +08:00
|
|
|
%val = call float @llvm.fma.f32(float %nega, float %b, float %negc)
|
2013-01-31 20:12:40 +08:00
|
|
|
; CHECK: fnmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST: fnmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
2013-01-31 20:12:40 +08:00
|
|
|
ret float %val
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define float @test_fnmsub(float %a, float %b, float %c) {
|
2013-07-12 22:54:12 +08:00
|
|
|
; CHECK-LABEL: test_fnmsub:
|
|
|
|
|
; CHECK-NOFAST-LABEL: test_fnmsub:
|
2013-01-31 20:12:40 +08:00
|
|
|
%negc = fsub float -0.0, %c
|
2013-12-24 08:40:10 +08:00
|
|
|
%val = call float @llvm.fma.f32(float %a, float %b, float %negc)
|
2013-01-31 20:12:40 +08:00
|
|
|
; CHECK: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
2013-01-31 20:12:40 +08:00
|
|
|
ret float %val
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define double @testd_fmadd(double %a, double %b, double %c) {
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: testd_fmadd:
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-NOFAST-LABEL: testd_fmadd:
|
2013-01-31 20:12:40 +08:00
|
|
|
%val = call double @llvm.fma.f64(double %a, double %b, double %c)
|
|
|
|
|
; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
2013-01-31 20:12:40 +08:00
|
|
|
ret double %val
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define double @testd_fmsub(double %a, double %b, double %c) {
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: testd_fmsub:
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-NOFAST-LABEL: testd_fmsub:
|
2013-01-31 20:12:40 +08:00
|
|
|
%nega = fsub double -0.0, %a
|
|
|
|
|
%val = call double @llvm.fma.f64(double %nega, double %b, double %c)
|
|
|
|
|
; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
2013-01-31 20:12:40 +08:00
|
|
|
ret double %val
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define double @testd_fnmadd(double %a, double %b, double %c) {
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: testd_fnmadd:
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-NOFAST-LABEL: testd_fnmadd:
|
2013-12-24 08:40:10 +08:00
|
|
|
%nega = fsub double -0.0, %a
|
2013-01-31 20:12:40 +08:00
|
|
|
%negc = fsub double -0.0, %c
|
2013-12-24 08:40:10 +08:00
|
|
|
%val = call double @llvm.fma.f64(double %nega, double %b, double %negc)
|
2013-01-31 20:12:40 +08:00
|
|
|
; CHECK: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
2013-01-31 20:12:40 +08:00
|
|
|
ret double %val
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define double @testd_fnmsub(double %a, double %b, double %c) {
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: testd_fnmsub:
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-NOFAST-LABEL: testd_fnmsub:
|
2013-01-31 20:12:40 +08:00
|
|
|
%negc = fsub double -0.0, %c
|
2013-12-24 08:40:10 +08:00
|
|
|
%val = call double @llvm.fma.f64(double %a, double %b, double %negc)
|
2013-01-31 20:12:40 +08:00
|
|
|
; CHECK: fnmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST: fnmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
2013-01-31 20:12:40 +08:00
|
|
|
ret double %val
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define float @test_fmadd_unfused(float %a, float %b, float %c) {
|
2013-07-12 22:54:12 +08:00
|
|
|
; CHECK-LABEL: test_fmadd_unfused:
|
|
|
|
|
; CHECK-NOFAST-LABEL: test_fmadd_unfused:
|
2013-01-31 20:12:40 +08:00
|
|
|
%prod = fmul float %b, %c
|
|
|
|
|
%sum = fadd float %a, %prod
|
|
|
|
|
; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST-NOT: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK-NOFAST: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK-NOFAST: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
2013-01-31 20:12:40 +08:00
|
|
|
ret float %sum
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define float @test_fmsub_unfused(float %a, float %b, float %c) {
|
2013-07-12 22:54:12 +08:00
|
|
|
; CHECK-LABEL: test_fmsub_unfused:
|
|
|
|
|
; CHECK-NOFAST-LABEL: test_fmsub_unfused:
|
2013-01-31 20:12:40 +08:00
|
|
|
%prod = fmul float %b, %c
|
|
|
|
|
%diff = fsub float %a, %prod
|
|
|
|
|
; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST-NOT: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK-NOFAST: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK-NOFAST: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
2013-01-31 20:12:40 +08:00
|
|
|
ret float %diff
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define float @test_fnmadd_unfused(float %a, float %b, float %c) {
|
2013-07-12 22:54:12 +08:00
|
|
|
; CHECK-LABEL: test_fnmadd_unfused:
|
|
|
|
|
; CHECK-NOFAST-LABEL: test_fnmadd_unfused:
|
2013-01-31 20:12:40 +08:00
|
|
|
%nega = fsub float -0.0, %a
|
|
|
|
|
%prod = fmul float %b, %c
|
2013-12-24 08:40:10 +08:00
|
|
|
%diff = fsub float %nega, %prod
|
2013-01-31 20:12:40 +08:00
|
|
|
; CHECK: fnmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST-NOT: fnmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK-NOFAST: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK-NOFAST: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
2013-12-24 08:40:10 +08:00
|
|
|
; CHECK-NOFAST: ret
|
|
|
|
|
ret float %diff
|
2013-01-31 20:12:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define float @test_fnmsub_unfused(float %a, float %b, float %c) {
|
2013-07-12 22:54:12 +08:00
|
|
|
; CHECK-LABEL: test_fnmsub_unfused:
|
|
|
|
|
; CHECK-NOFAST-LABEL: test_fnmsub_unfused:
|
2013-01-31 20:12:40 +08:00
|
|
|
%nega = fsub float -0.0, %a
|
|
|
|
|
%prod = fmul float %b, %c
|
2013-12-24 08:40:10 +08:00
|
|
|
%sum = fadd float %nega, %prod
|
2013-01-31 20:12:40 +08:00
|
|
|
; CHECK: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
llvm-svn: 185956
2013-07-10 02:16:56 +08:00
|
|
|
; CHECK-NOFAST-NOT: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
2013-12-24 08:40:10 +08:00
|
|
|
; CHECK-NOFAST: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK-NOFAST: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
ret float %sum
|
2013-01-31 20:12:40 +08:00
|
|
|
}
|
2013-12-24 08:40:10 +08:00
|
|
|
|
2013-12-24 08:47:29 +08:00
|
|
|
; Another set of tests that check for multiply single use
|
|
|
|
|
|
|
|
|
|
define float @test_fmadd_unfused_su(float %a, float %b, float %c) {
|
|
|
|
|
; CHECK-LABEL: test_fmadd_unfused_su:
|
|
|
|
|
%prod = fmul float %b, %c
|
|
|
|
|
%sum = fadd float %a, %prod
|
|
|
|
|
%res = fadd float %sum, %prod
|
|
|
|
|
; CHECK-NOT: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
ret float %res
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define float @test_fmsub_unfused_su(float %a, float %b, float %c) {
|
|
|
|
|
; CHECK-LABEL: test_fmsub_unfused_su:
|
|
|
|
|
%prod = fmul float %b, %c
|
|
|
|
|
%diff = fsub float %a, %prod
|
|
|
|
|
%res = fsub float %diff, %prod
|
|
|
|
|
; CHECK-NOT: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
; CHECK: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
|
|
|
|
ret float %res
|
|
|
|
|
}
|
|
|
|
|
|
