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[X86][AVX] Added AVX1 target shuffle combine tests llvm-svn: 262132
2016-02-27 20:33:08 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Fix two more places to prefer VPERMQ/PD over VPERM2X128 when AVX2 is enabled The shuffle combining and lowerVectorShuffleAsLanePermuteAndBlend were both still trying to use VPERM2XF128 for unary shuffles when AVX2 is enabled. VPERM2X128 takes two inputs meaning when we use it for a unary shuffle one of those inputs is left undefined creating a false dependency on whatever register gets allocated there. If we have VPERMQ/PD we should prefer those since they only have a single input. Differential Revision: https://reviews.llvm.org/D37947 llvm-svn: 313542
2017-09-19 00:39:49 +08:00
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX --check-prefix=X32-AVX1
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX --check-prefix=X32-AVX2
Change prefix in vector-shuffle-combining-avx.patch to reduce test size. llvm-svn: 309315
2017-07-28 03:47:35 +08:00
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX512
[X86] Fix two more places to prefer VPERMQ/PD over VPERM2X128 when AVX2 is enabled The shuffle combining and lowerVectorShuffleAsLanePermuteAndBlend were both still trying to use VPERM2XF128 for unary shuffles when AVX2 is enabled. VPERM2X128 takes two inputs meaning when we use it for a unary shuffle one of those inputs is left undefined creating a false dependency on whatever register gets allocated there. If we have VPERMQ/PD we should prefer those since they only have a single input. Differential Revision: https://reviews.llvm.org/D37947 llvm-svn: 313542
2017-09-19 00:39:49 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX --check-prefix=X64-AVX1
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX --check-prefix=X64-AVX2
Change prefix in vector-shuffle-combining-avx.patch to reduce test size. llvm-svn: 309315
2017-07-28 03:47:35 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512
[X86][AVX] Added AVX1 target shuffle combine tests llvm-svn: 262132
2016-02-27 20:33:08 +08:00
;
; Combine tests involving AVX target shuffles
declare <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float>, i8)
declare <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float>, i8)
declare <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double>, i8)
declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8)
declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>)
declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>)
declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>)
declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i64>)
declare <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32>, <8 x i32>, i8)
declare <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float>, <8 x float>, i8)
declare <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double>, <4 x double>, i8)
[X86][AVX] Fixed issue where a long chain of shuffles could attempt to combine to a single (illegal) PSHUFB instruction. Its not enough that we test for SSSE3 - that's only OK for 128-bit vectors - we also need to test for AVX2 / AVX512BW for 256/512 bit vector cases. llvm-svn: 263239
2016-03-11 22:39:10 +08:00
define <4 x float> @combine_vpermilvar_4f32_identity(<4 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f32_identity:
; X32: # BB#0:
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f32_identity:
; X64: # BB#0:
; X64-NEXT: retq
[X86][AVX] Added AVX1 target shuffle combine tests llvm-svn: 262132
2016-02-27 20:33:08 +08:00
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
%2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %1, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
ret <4 x float> %2
}
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
define <4 x float> @combine_vpermilvar_4f32_movddup(<4 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f32_movddup:
; X32: # BB#0:
; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f32_movddup:
; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X64-NEXT: retq
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 0, i32 1, i32 0, i32 1>)
ret <4 x float> %1
}
[X86][AVX] Added some shuffle combine from load tests As discussed on D19198 - we need to check what happens when we shuffle with different value type to the load llvm-svn: 269068
2016-05-11 00:08:24 +08:00
define <4 x float> @combine_vpermilvar_4f32_movddup_load(<4 x float> *%a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f32_movddup_load:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f32_movddup_load:
; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; X64-NEXT: retq
[X86][AVX] Added some shuffle combine from load tests As discussed on D19198 - we need to check what happens when we shuffle with different value type to the load llvm-svn: 269068
2016-05-11 00:08:24 +08:00
%1 = load <4 x float>, <4 x float> *%a0
%2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %1, <4 x i32> <i32 0, i32 1, i32 0, i32 1>)
ret <4 x float> %2
}
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
define <4 x float> @combine_vpermilvar_4f32_movshdup(<4 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f32_movshdup:
; X32: # BB#0:
; X32-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f32_movshdup:
; X64: # BB#0:
; X64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X64-NEXT: retq
[X86][SSE] Allow target shuffle combining to match masks with SM_Sentinel values We currently only allow exact matches of shuffle mask patterns during target shuffle combining. This patch relaxes this to permit SM_SentinelUndef in the combined shuffle to always be accepted as well as allowing exact matching of the SM_SentinelZero value. I've adjusted some tests that were requiring exact shuffle masks to now include undef values. Differential Revision: http://reviews.llvm.org/D21495 llvm-svn: 273119
2016-06-20 02:03:52 +08:00
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 undef, i32 1, i32 3, i32 3>)
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
ret <4 x float> %1
}
define <4 x float> @combine_vpermilvar_4f32_movsldup(<4 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f32_movsldup:
; X32: # BB#0:
; X32-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f32_movsldup:
; X64: # BB#0:
; X64-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X64-NEXT: retq
[X86][SSE] Allow target shuffle combining to match masks with SM_Sentinel values We currently only allow exact matches of shuffle mask patterns during target shuffle combining. This patch relaxes this to permit SM_SentinelUndef in the combined shuffle to always be accepted as well as allowing exact matching of the SM_SentinelZero value. I've adjusted some tests that were requiring exact shuffle masks to now include undef values. Differential Revision: http://reviews.llvm.org/D21495 llvm-svn: 273119
2016-06-20 02:03:52 +08:00
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 0, i32 0, i32 2, i32 undef>)
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
ret <4 x float> %1
}
define <4 x float> @combine_vpermilvar_4f32_unpckh(<4 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f32_unpckh:
; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f32_unpckh:
; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X64-NEXT: retq
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 2, i32 2, i32 3, i32 3>)
ret <4 x float> %1
}
define <4 x float> @combine_vpermilvar_4f32_unpckl(<4 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f32_unpckl:
; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f32_unpckl:
; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X64-NEXT: retq
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 0, i32 0, i32 1, i32 1>)
ret <4 x float> %1
}
[X86][AVX] Fixed issue where a long chain of shuffles could attempt to combine to a single (illegal) PSHUFB instruction. Its not enough that we test for SSSE3 - that's only OK for 128-bit vectors - we also need to test for AVX2 / AVX512BW for 256/512 bit vector cases. llvm-svn: 263239
2016-03-11 22:39:10 +08:00
define <8 x float> @combine_vpermilvar_8f32_identity(<8 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_8f32_identity:
; X32: # BB#0:
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_8f32_identity:
; X64: # BB#0:
; X64-NEXT: retq
[X86][SSE] Allow target shuffle combining to match masks with SM_Sentinel values We currently only allow exact matches of shuffle mask patterns during target shuffle combining. This patch relaxes this to permit SM_SentinelUndef in the combined shuffle to always be accepted as well as allowing exact matching of the SM_SentinelZero value. I've adjusted some tests that were requiring exact shuffle masks to now include undef values. Differential Revision: http://reviews.llvm.org/D21495 llvm-svn: 273119
2016-06-20 02:03:52 +08:00
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 2, i32 3, i32 0, i32 undef>)
[X86][AVX] Added AVX1 target shuffle combine tests llvm-svn: 262132
2016-02-27 20:33:08 +08:00
%2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 2, i32 3, i32 0, i32 1>)
ret <8 x float> %2
}
[X86][AVX] Add support for target shuffle combining to VPERMILPS variable shuffle mask Added AVX512F VPERMILPS shuffle decoding support llvm-svn: 275270
2016-07-13 23:10:43 +08:00
define <8 x float> @combine_vpermilvar_8f32_10326u4u(<8 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_8f32_10326u4u:
; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_8f32_10326u4u:
; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u]
; X64-NEXT: retq
[X86][AVX] Add support for target shuffle combining to VPERMILPS variable shuffle mask Added AVX512F VPERMILPS shuffle decoding support llvm-svn: 275270
2016-07-13 23:10:43 +08:00
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 0, i32 1, i32 2, i32 undef>)
%2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 undef>)
ret <8 x float> %2
}
[X86][AVX] Add support for target shuffle combining to VPERM2F128/VPERM2I128 llvm-svn: 275212
2016-07-13 04:27:32 +08:00
define <8 x float> @combine_vpermilvar_vperm2f128_8f32(<8 x float> %a0) {
[X86] Fix two more places to prefer VPERMQ/PD over VPERM2X128 when AVX2 is enabled The shuffle combining and lowerVectorShuffleAsLanePermuteAndBlend were both still trying to use VPERM2XF128 for unary shuffles when AVX2 is enabled. VPERM2X128 takes two inputs meaning when we use it for a unary shuffle one of those inputs is left undefined creating a false dependency on whatever register gets allocated there. If we have VPERMQ/PD we should prefer those since they only have a single input. Differential Revision: https://reviews.llvm.org/D37947 llvm-svn: 313542
2017-09-19 00:39:49 +08:00
; X32-AVX1-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X32-AVX1-NEXT: retl
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
;
[X86] Fix two more places to prefer VPERMQ/PD over VPERM2X128 when AVX2 is enabled The shuffle combining and lowerVectorShuffleAsLanePermuteAndBlend were both still trying to use VPERM2XF128 for unary shuffles when AVX2 is enabled. VPERM2X128 takes two inputs meaning when we use it for a unary shuffle one of those inputs is left undefined creating a false dependency on whatever register gets allocated there. If we have VPERMQ/PD we should prefer those since they only have a single input. Differential Revision: https://reviews.llvm.org/D37947 llvm-svn: 313542
2017-09-19 00:39:49 +08:00
; X32-AVX2-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X32-AVX2-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X32-AVX512-NEXT: retl
;
; X64-AVX1-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X64-AVX1-NEXT: retq
;
; X64-AVX2-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X64-AVX2-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X64-AVX512-NEXT: retq
[X86][AVX] Add support for target shuffle combining to VPERM2F128/VPERM2I128 llvm-svn: 275212
2016-07-13 04:27:32 +08:00
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
%2 = shufflevector <8 x float> %1, <8 x float> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
%3 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %2, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
ret <8 x float> %3
}
define <8 x float> @combine_vpermilvar_vperm2f128_zero_8f32(<8 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; X32: # BB#0:
; X32-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; X64: # BB#0:
; X64-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; X64-NEXT: retq
[X86][AVX] Add support for target shuffle combining to VPERM2F128/VPERM2I128 llvm-svn: 275212
2016-07-13 04:27:32 +08:00
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
%2 = shufflevector <8 x float> %1, <8 x float> zeroinitializer, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3>
%3 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %2, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
ret <8 x float> %3
}
[X86][AVX] Add 128-bit wide shuffle tests that should combine to blend-with-zero llvm-svn: 275402
2016-07-14 20:21:40 +08:00
define <4 x double> @combine_vperm2f128_vpermilvar_as_vpblendpd(<4 x double> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; X32: # BB#0:
[X86] SET0 to use XMM registers where possible PR26018 PR32862 Differential Revision: https://reviews.llvm.org/D35839 llvm-svn: 309298
2017-07-28 01:47:01 +08:00
; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; X32-NEXT: retl
;
; X64-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; X64: # BB#0:
[X86] SET0 to use XMM registers where possible PR26018 PR32862 Differential Revision: https://reviews.llvm.org/D35839 llvm-svn: 309298
2017-07-28 01:47:01 +08:00
; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; X64-NEXT: retq
[X86][AVX] Add 128-bit wide shuffle tests that should combine to blend-with-zero llvm-svn: 275402
2016-07-14 20:21:40 +08:00
%1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 2, i64 0, i64 2, i64 0>)
%2 = shufflevector <4 x double> %1, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
%3 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %2, <4 x i64> <i64 2, i64 0, i64 2, i64 0>)
ret <4 x double> %3
}
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
define <8 x float> @combine_vpermilvar_8f32_movddup(<8 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_8f32_movddup:
; X32: # BB#0:
; X32-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_8f32_movddup:
; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X64-NEXT: retq
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>)
ret <8 x float> %1
}
[X86][AVX] Added some shuffle combine from load tests As discussed on D19198 - we need to check what happens when we shuffle with different value type to the load llvm-svn: 269068
2016-05-11 00:08:24 +08:00
define <8 x float> @combine_vpermilvar_8f32_movddup_load(<8 x float> *%a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_8f32_movddup_load:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_8f32_movddup_load:
; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
; X64-NEXT: retq
[X86][AVX] Added some shuffle combine from load tests As discussed on D19198 - we need to check what happens when we shuffle with different value type to the load llvm-svn: 269068
2016-05-11 00:08:24 +08:00
%1 = load <8 x float>, <8 x float> *%a0
%2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>)
ret <8 x float> %2
}
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
define <8 x float> @combine_vpermilvar_8f32_movshdup(<8 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_8f32_movshdup:
; X32: # BB#0:
; X32-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_8f32_movshdup:
; X64: # BB#0:
; X64-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
; X64-NEXT: retq
[X86][SSE] Allow target shuffle combining to match masks with SM_Sentinel values We currently only allow exact matches of shuffle mask patterns during target shuffle combining. This patch relaxes this to permit SM_SentinelUndef in the combined shuffle to always be accepted as well as allowing exact matching of the SM_SentinelZero value. I've adjusted some tests that were requiring exact shuffle masks to now include undef values. Differential Revision: http://reviews.llvm.org/D21495 llvm-svn: 273119
2016-06-20 02:03:52 +08:00
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 5, i32 7, i32 7>)
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
ret <8 x float> %1
}
define <8 x float> @combine_vpermilvar_8f32_movsldup(<8 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_8f32_movsldup:
; X32: # BB#0:
; X32-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_8f32_movsldup:
; X64: # BB#0:
; X64-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
; X64-NEXT: retq
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>)
ret <8 x float> %1
}
[X86][AVX] Fixed issue where a long chain of shuffles could attempt to combine to a single (illegal) PSHUFB instruction. Its not enough that we test for SSSE3 - that's only OK for 128-bit vectors - we also need to test for AVX2 / AVX512BW for 256/512 bit vector cases. llvm-svn: 263239
2016-03-11 22:39:10 +08:00
define <2 x double> @combine_vpermilvar_2f64_identity(<2 x double> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_2f64_identity:
; X32: # BB#0:
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_2f64_identity:
; X64: # BB#0:
; X64-NEXT: retq
[X86][AVX] vpermilvar.pd mask element indices only use bit1 llvm-svn: 262134
2016-02-27 20:51:46 +08:00
%1 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> <i64 2, i64 0>)
%2 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %1, <2 x i64> <i64 2, i64 0>)
[X86][AVX] Added AVX1 target shuffle combine tests llvm-svn: 262132
2016-02-27 20:33:08 +08:00
ret <2 x double> %2
}
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
define <2 x double> @combine_vpermilvar_2f64_movddup(<2 x double> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_2f64_movddup:
; X32: # BB#0:
; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_2f64_movddup:
; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X64-NEXT: retq
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
%1 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> <i64 0, i64 0>)
ret <2 x double> %1
}
[X86][AVX] Fixed issue where a long chain of shuffles could attempt to combine to a single (illegal) PSHUFB instruction. Its not enough that we test for SSSE3 - that's only OK for 128-bit vectors - we also need to test for AVX2 / AVX512BW for 256/512 bit vector cases. llvm-svn: 263239
2016-03-11 22:39:10 +08:00
define <4 x double> @combine_vpermilvar_4f64_identity(<4 x double> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f64_identity:
; X32: # BB#0:
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f64_identity:
; X64: # BB#0:
; X64-NEXT: retq
[X86][AVX] vpermilvar.pd mask element indices only use bit1 llvm-svn: 262134
2016-02-27 20:51:46 +08:00
%1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 2, i64 0, i64 2, i64 0>)
%2 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %1, <4 x i64> <i64 2, i64 0, i64 2, i64 0>)
[X86][AVX] Added AVX1 target shuffle combine tests llvm-svn: 262132
2016-02-27 20:33:08 +08:00
ret <4 x double> %2
}
[X86][AVX] Fixed issue where a long chain of shuffles could attempt to combine to a single (illegal) PSHUFB instruction. Its not enough that we test for SSSE3 - that's only OK for 128-bit vectors - we also need to test for AVX2 / AVX512BW for 256/512 bit vector cases. llvm-svn: 263239
2016-03-11 22:39:10 +08:00
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
define <4 x double> @combine_vpermilvar_4f64_movddup(<4 x double> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f64_movddup:
; X32: # BB#0:
; X32-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f64_movddup:
; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X64-NEXT: retq
[X86][AVX] Add shuffle combine tests for MOVDDUP/MOVSHDUP/MOVSLDUP 128, 256 and 512 bit implementations (some not yet supported by combineX86ShuffleChain) llvm-svn: 266535
2016-04-17 04:30:59 +08:00
%1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 0, i64 0, i64 4, i64 4>)
ret <4 x double> %1
}
[X86][AVX] Fixed issue where a long chain of shuffles could attempt to combine to a single (illegal) PSHUFB instruction. Its not enough that we test for SSSE3 - that's only OK for 128-bit vectors - we also need to test for AVX2 / AVX512BW for 256/512 bit vector cases. llvm-svn: 263239
2016-03-11 22:39:10 +08:00
define <4 x float> @combine_vpermilvar_4f32_4stage(<4 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f32_4stage:
; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f32_4stage:
; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
; X64-NEXT: retq
[X86][AVX] Fixed issue where a long chain of shuffles could attempt to combine to a single (illegal) PSHUFB instruction. Its not enough that we test for SSSE3 - that's only OK for 128-bit vectors - we also need to test for AVX2 / AVX512BW for 256/512 bit vector cases. llvm-svn: 263239
2016-03-11 22:39:10 +08:00
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
%2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %1, <4 x i32> <i32 2, i32 3, i32 0, i32 1>)
%3 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>)
%4 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %3, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
ret <4 x float> %4
}
define <8 x float> @combine_vpermilvar_8f32_4stage(<8 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_8f32_4stage:
; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_8f32_4stage:
; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; X64-NEXT: retq
[X86][AVX] Fixed issue where a long chain of shuffles could attempt to combine to a single (illegal) PSHUFB instruction. Its not enough that we test for SSSE3 - that's only OK for 128-bit vectors - we also need to test for AVX2 / AVX512BW for 256/512 bit vector cases. llvm-svn: 263239
2016-03-11 22:39:10 +08:00
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
%2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1>)
%3 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %2, <8 x i32> <i32 0, i32 2, i32 1, i32 3, i32 0, i32 2, i32 1, i32 3>)
%4 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %3, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
ret <8 x float> %4
}
[X86][AVX] Added combine test that should simplify to insertps llvm-svn: 274884
2016-07-09 01:01:42 +08:00
define <4 x float> @combine_vpermilvar_4f32_as_insertps(<4 x float> %a0) {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: combine_vpermilvar_4f32_as_insertps:
; X32: # BB#0:
; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero
; X32-NEXT: retl
;
; X64-LABEL: combine_vpermilvar_4f32_as_insertps:
; X64: # BB#0:
; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero
; X64-NEXT: retq
[X86][AVX] Added combine test that should simplify to insertps llvm-svn: 274884
2016-07-09 01:01:42 +08:00
%1 = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
%2 = shufflevector <4 x float> %1, <4 x float> zeroinitializer, <4 x i32> <i32 2, i32 4, i32 1, i32 4>
ret <4 x float> %2
}
[X86][AVX] Add target shuffle constant folding tests llvm-svn: 281829
2016-09-18 01:41:14 +08:00
define <2 x double> @constant_fold_vpermilvar_pd() {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: constant_fold_vpermilvar_pd:
; X32: # BB#0:
[X86][SSE] Add support for target shuffle constant folding Initial support for target shuffle constant folding in cases where all shuffle inputs are constant. We may be able to relax this and merge shuffles with only some constant inputs in the future. I've added the helper function getTargetConstantBitsFromNode (based off a similar function in X86ShuffleDecodeConstantPool.cpp) that could be reused for other cases requiring constant vector extraction. Differential Revision: https://reviews.llvm.org/D27220 llvm-svn: 288250
2016-12-01 00:33:46 +08:00
; X32-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00]
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-NEXT: retl
;
; X64-LABEL: constant_fold_vpermilvar_pd:
; X64: # BB#0:
[X86][SSE] Add support for target shuffle constant folding Initial support for target shuffle constant folding in cases where all shuffle inputs are constant. We may be able to relax this and merge shuffles with only some constant inputs in the future. I've added the helper function getTargetConstantBitsFromNode (based off a similar function in X86ShuffleDecodeConstantPool.cpp) that could be reused for other cases requiring constant vector extraction. Differential Revision: https://reviews.llvm.org/D27220 llvm-svn: 288250
2016-12-01 00:33:46 +08:00
; X64-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00]
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X64-NEXT: retq
[X86][AVX] Add target shuffle constant folding tests llvm-svn: 281829
2016-09-18 01:41:14 +08:00
%1 = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> <double 1.0, double 2.0>, <2 x i64> <i64 2, i64 0>)
ret <2 x double> %1
}
define <4 x double> @constant_fold_vpermilvar_pd_256() {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: constant_fold_vpermilvar_pd_256:
; X32: # BB#0:
[X86][SSE] Add support for target shuffle constant folding Initial support for target shuffle constant folding in cases where all shuffle inputs are constant. We may be able to relax this and merge shuffles with only some constant inputs in the future. I've added the helper function getTargetConstantBitsFromNode (based off a similar function in X86ShuffleDecodeConstantPool.cpp) that could be reused for other cases requiring constant vector extraction. Differential Revision: https://reviews.llvm.org/D27220 llvm-svn: 288250
2016-12-01 00:33:46 +08:00
; X32-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00]
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-NEXT: retl
;
; X64-LABEL: constant_fold_vpermilvar_pd_256:
; X64: # BB#0:
[X86][SSE] Add support for target shuffle constant folding Initial support for target shuffle constant folding in cases where all shuffle inputs are constant. We may be able to relax this and merge shuffles with only some constant inputs in the future. I've added the helper function getTargetConstantBitsFromNode (based off a similar function in X86ShuffleDecodeConstantPool.cpp) that could be reused for other cases requiring constant vector extraction. Differential Revision: https://reviews.llvm.org/D27220 llvm-svn: 288250
2016-12-01 00:33:46 +08:00
; X64-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00]
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X64-NEXT: retq
[X86][AVX] Add target shuffle constant folding tests llvm-svn: 281829
2016-09-18 01:41:14 +08:00
%1 = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, <4 x i64> <i64 2, i64 0, i64 0, i64 2>)
ret <4 x double> %1
}
define <4 x float> @constant_fold_vpermilvar_ps() {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: constant_fold_vpermilvar_ps:
; X32: # BB#0:
[X86][SSE] Add support for target shuffle constant folding Initial support for target shuffle constant folding in cases where all shuffle inputs are constant. We may be able to relax this and merge shuffles with only some constant inputs in the future. I've added the helper function getTargetConstantBitsFromNode (based off a similar function in X86ShuffleDecodeConstantPool.cpp) that could be reused for other cases requiring constant vector extraction. Differential Revision: https://reviews.llvm.org/D27220 llvm-svn: 288250
2016-12-01 00:33:46 +08:00
; X32-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00]
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-NEXT: retl
;
; X64-LABEL: constant_fold_vpermilvar_ps:
; X64: # BB#0:
[X86][SSE] Add support for target shuffle constant folding Initial support for target shuffle constant folding in cases where all shuffle inputs are constant. We may be able to relax this and merge shuffles with only some constant inputs in the future. I've added the helper function getTargetConstantBitsFromNode (based off a similar function in X86ShuffleDecodeConstantPool.cpp) that could be reused for other cases requiring constant vector extraction. Differential Revision: https://reviews.llvm.org/D27220 llvm-svn: 288250
2016-12-01 00:33:46 +08:00
; X64-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00]
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X64-NEXT: retq
[X86][AVX] Add target shuffle constant folding tests llvm-svn: 281829
2016-09-18 01:41:14 +08:00
%1 = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, <4 x i32> <i32 3, i32 0, i32 2, i32 1>)
ret <4 x float> %1
}
define <8 x float> @constant_fold_vpermilvar_ps_256() {
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-LABEL: constant_fold_vpermilvar_ps_256:
; X32: # BB#0:
[X86][SSE] Add support for target shuffle constant folding Initial support for target shuffle constant folding in cases where all shuffle inputs are constant. We may be able to relax this and merge shuffles with only some constant inputs in the future. I've added the helper function getTargetConstantBitsFromNode (based off a similar function in X86ShuffleDecodeConstantPool.cpp) that could be reused for other cases requiring constant vector extraction. Differential Revision: https://reviews.llvm.org/D27220 llvm-svn: 288250
2016-12-01 00:33:46 +08:00
; X32-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00]
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X32-NEXT: retl
;
; X64-LABEL: constant_fold_vpermilvar_ps_256:
; X64: # BB#0:
[X86][SSE] Add support for target shuffle constant folding Initial support for target shuffle constant folding in cases where all shuffle inputs are constant. We may be able to relax this and merge shuffles with only some constant inputs in the future. I've added the helper function getTargetConstantBitsFromNode (based off a similar function in X86ShuffleDecodeConstantPool.cpp) that could be reused for other cases requiring constant vector extraction. Differential Revision: https://reviews.llvm.org/D27220 llvm-svn: 288250
2016-12-01 00:33:46 +08:00
; X64-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00]
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets llvm-svn: 281833
2016-09-18 02:42:41 +08:00
; X64-NEXT: retq
[X86][AVX] Add target shuffle constant folding tests llvm-svn: 281829
2016-09-18 01:41:14 +08:00
%1 = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, <8 x i32> <i32 4, i32 0, i32 2, i32 1, i32 0, i32 1, i32 1, i32 1>)
ret <8 x float> %1
}