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llvm-project/llvm/test/CodeGen/X86/live-range-nosubreg.ll

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X86: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309774
2017-08-02 08:28:10 +08:00
; RUN: llc < %s
Do not use MRI::getMaxLaneMaskForVReg as a mask covering whole register MRI::getMaxLaneMaskForVReg does not always cover the whole register. For example, on X86 the upper 16 bits of EAX cannot be accessed via any subregister. Consequently, there is no lane mask that only covers that part of EAX. The getMaxLaneMaskForVReg will return the union of the lane masks for all subregisters, and in case of EAX, that union will not cover the upper 16 bits. This fixes https://llvm.org/bugs/show_bug.cgi?id=29132 llvm-svn: 279969
2016-08-29 21:15:35 +08:00
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. Recommiting with compiler time improvements Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner. * Simplify Consecutive Merge Store Candidate Search Now that address aliasing is much less conservative, push through simplified store merging search and chain alias analysis which only checks for parallel stores through the chain subgraph. This is cleaner as the separation of non-interfering loads/stores from the store-merging logic. When merging stores search up the chain through a single load, and finds all possible stores by looking down from through a load and a TokenFactor to all stores visited. This improves the quality of the output SelectionDAG and the output Codegen (save perhaps for some ARM cases where we correctly constructs wider loads, but then promotes them to float operations which appear but requires more expensive constant generation). Some minor peephole optimizations to deal with improved SubDAG shapes (listed below) Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seems sufficient to not cause regressions in tests. 5. Remove Chain dependencies of Memory operations on CopyfromReg nodes as these are captured by data dependence 6. Forward loads-store values through tokenfactors containing {CopyToReg,CopyFromReg} Values. 7. Peephole to convert buildvector of extract_vector_elt to extract_subvector if possible (see CodeGen/AArch64/store-merge.ll) 8. Store merging for the ARM target is restricted to 32-bit as some in some contexts invalid 64-bit operations are being generated. This can be removed once appropriate checks are added. This finishes the change Matt Arsenault started in r246307 and jyknight's original patch. Many tests required some changes as memory operations are now reorderable, improving load-store forwarding. One test in particular is worth noting: CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store forwarding converts a load-store pair into a parallel store and a memory-realized bitcast of the same value. However, because we lose the sharing of the explicit and implicit store values we must create another local store. A similar transformation happens before SelectionDAG as well. Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle llvm-svn: 297695
2017-03-14 08:34:14 +08:00
; This testcase used to crash. See PR29132.
Do not use MRI::getMaxLaneMaskForVReg as a mask covering whole register MRI::getMaxLaneMaskForVReg does not always cover the whole register. For example, on X86 the upper 16 bits of EAX cannot be accessed via any subregister. Consequently, there is no lane mask that only covers that part of EAX. The getMaxLaneMaskForVReg will return the union of the lane masks for all subregisters, and in case of EAX, that union will not cover the upper 16 bits. This fixes https://llvm.org/bugs/show_bug.cgi?id=29132 llvm-svn: 279969
2016-08-29 21:15:35 +08:00
target triple = "x86_64-unknown-linux-gnu"
@a = common local_unnamed_addr global i16 0, align 2
@c = common global i32 0, align 4
@d = common local_unnamed_addr global i8 0, align 1
@b = common global i32 0, align 4
; Function Attrs: norecurse nounwind optsize uwtable
define i32 @main() local_unnamed_addr #0 {
entry:
%0 = load volatile i32, i32* @c, align 4
%tobool = icmp eq i32 %0, 0
%1 = load i16, i16* @a, align 2
br i1 %tobool, label %lor.rhs, label %lor.end
lor.rhs: ; preds = %entry
%inc = add i16 %1, 1
store i16 %inc, i16* @a, align 2
br label %lor.end
lor.end: ; preds = %entry, %lor.rhs
%2 = phi i16 [ %inc, %lor.rhs ], [ %1, %entry ]
%dec = add i16 %2, -1
store i16 %dec, i16* @a, align 2
%3 = load i8, i8* @d, align 1
%sub = sub i8 0, %3
%tobool4 = icmp eq i16 %dec, 0
br i1 %tobool4, label %land.end, label %land.rhs
land.rhs: ; preds = %lor.end
%4 = load volatile i32, i32* @b, align 4
%tobool5 = icmp ne i32 %4, 0
br label %land.end
land.end: ; preds = %lor.end, %land.rhs
%5 = phi i1 [ false, %lor.end ], [ %tobool5, %land.rhs ]
%land.ext = zext i1 %5 to i8
%or = or i8 %land.ext, %sub
store i8 %or, i8* @d, align 1
ret i32 0
}
attributes #0 = { norecurse nounwind optsize uwtable "target-cpu"="x86-64" }