forked from OSchip/llvm-project
78 lines
3.3 KiB
Plaintext
78 lines
3.3 KiB
Plaintext
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# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
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# CGN-LABEL: name: flat_load_clustering
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# GCN: FLAT_LOAD_DWORD
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# GCN-NEXT: FLAT_LOAD_DWORD
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--- |
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define amdgpu_kernel void @flat_load_clustering(i32 addrspace(1)* nocapture %arg, i32 addrspace(2)* nocapture readonly %arg1) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%idxprom = sext i32 %tid to i64
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%gep1 = getelementptr inbounds i32, i32 addrspace(2)* %arg1, i64 %idxprom
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%load1 = load i32, i32 addrspace(2)* %gep1, align 4
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%gep2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %idxprom
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%gep34 = getelementptr inbounds i32, i32 addrspace(2)* %gep1, i64 4
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%load2 = load i32, i32 addrspace(2)* %gep34, align 4
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%gep4 = getelementptr inbounds i32, i32 addrspace(1)* %gep2, i64 4
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store i32 %load1, i32 addrspace(1)* %gep2, align 4
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store i32 %load2, i32 addrspace(1)* %gep4, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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...
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---
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name: flat_load_clustering
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: sgpr_64 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: vgpr_32 }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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- { id: 8, class: vgpr_32 }
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- { id: 9, class: vreg_64 }
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- { id: 10, class: vreg_64 }
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- { id: 11, class: vgpr_32 }
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- { id: 12, class: vreg_64 }
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- { id: 13, class: vreg_64 }
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liveins:
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- { reg: '%vgpr0', virtual-reg: '%0' }
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- { reg: '%sgpr4_sgpr5', virtual-reg: '%1' }
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body: |
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bb.0.bb:
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liveins: %vgpr0, %sgpr4_sgpr5
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%1 = COPY %sgpr4_sgpr5
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%0 = COPY %vgpr0
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%3 = S_LOAD_DWORDX2_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%4 = S_LOAD_DWORDX2_IMM %1, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%7 = V_LSHLREV_B32_e32 2, %0, implicit %exec
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%2 = V_MOV_B32_e32 0, implicit %exec
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undef %12.sub0 = V_ADD_I32_e32 %4.sub0, %7, implicit-def %vcc, implicit %exec
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%11 = COPY %4.sub1
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%12.sub1 = V_ADDC_U32_e32 %11, %2, implicit-def dead %vcc, implicit killed %vcc, implicit %exec
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%5 = FLAT_LOAD_DWORD %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.gep1)
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undef %9.sub0 = V_ADD_I32_e32 %3.sub0, %7, implicit-def %vcc, implicit %exec
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%8 = COPY %3.sub1
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%9.sub1 = V_ADDC_U32_e32 %8, %2, implicit-def dead %vcc, implicit killed %vcc, implicit %exec
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undef %13.sub0 = V_ADD_I32_e32 16, %12.sub0, implicit-def %vcc, implicit %exec
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%13.sub1 = V_ADDC_U32_e32 %12.sub1, %2, implicit-def dead %vcc, implicit killed %vcc, implicit %exec
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%6 = FLAT_LOAD_DWORD %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.gep34)
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undef %10.sub0 = V_ADD_I32_e32 16, %9.sub0, implicit-def %vcc, implicit %exec
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%10.sub1 = V_ADDC_U32_e32 %9.sub1, %2, implicit-def dead %vcc, implicit killed %vcc, implicit %exec
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FLAT_STORE_DWORD %9, %5, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.gep2)
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FLAT_STORE_DWORD %10, %6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.gep4)
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S_ENDPGM
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...
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