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llvm-project/llvm/test/CodeGen/Mips/msa/elm_copy.ll

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[mips][msa] Summarize tests Adds a comment to the start of each test summarizing the area the test covers. llvm-svn: 189465
2013-08-28 18:02:29 +08:00
; Test the MSA intrinsics that are encoded with the ELM instruction format and
; are element extraction operations.
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
@llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_copy_s_b_RES = global i32 0, align 16
define void @llvm_mips_copy_s_b_test() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_copy_s_b_ARG1
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
%1 = tail call i32 @llvm.mips.copy.s.b(<16 x i8> %0, i32 1)
store i32 %1, i32* @llvm_mips_copy_s_b_RES
ret void
}
declare i32 @llvm.mips.copy.s.b(<16 x i8>, i32) nounwind
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY: llvm_mips_copy_s_b_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_b_ARG1)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_ARG1)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])
; MIPS-ANY-DAG: copy_s.b [[RD:\$[0-9]+]], [[WS]][1]
; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_RES)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
; MIPS-ANY: .size llvm_mips_copy_s_b_test
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
;
@llvm_mips_copy_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_copy_s_h_RES = global i32 0, align 16
define void @llvm_mips_copy_s_h_test() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_copy_s_h_ARG1
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
%1 = tail call i32 @llvm.mips.copy.s.h(<8 x i16> %0, i32 1)
store i32 %1, i32* @llvm_mips_copy_s_h_RES
ret void
}
declare i32 @llvm.mips.copy.s.h(<8 x i16>, i32) nounwind
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY: llvm_mips_copy_s_h_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_h_ARG1)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_ARG1)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])
; MIPS-ANY-DAG: copy_s.h [[RD:\$[0-9]+]], [[WS]][1]
; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_RES)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
; MIPS-ANY: .size llvm_mips_copy_s_h_test
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
;
@llvm_mips_copy_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@llvm_mips_copy_s_w_RES = global i32 0, align 16
define void @llvm_mips_copy_s_w_test() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_copy_s_w_ARG1
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
%1 = tail call i32 @llvm.mips.copy.s.w(<4 x i32> %0, i32 1)
store i32 %1, i32* @llvm_mips_copy_s_w_RES
ret void
}
declare i32 @llvm.mips.copy.s.w(<4 x i32>, i32) nounwind
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY: llvm_mips_copy_s_w_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_w_ARG1)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_ARG1)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
; MIPS-ANY-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1]
; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_RES)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
; MIPS-ANY: .size llvm_mips_copy_s_w_test
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
;
[mips][msa] Implemented copy_[us].d intrinsic. This intrinsic is lowered into equivalent copy_s.w instructions during legalization. llvm-svn: 191518
2013-09-27 21:04:21 +08:00
@llvm_mips_copy_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
@llvm_mips_copy_s_d_RES = global i64 0, align 16
define void @llvm_mips_copy_s_d_test() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_copy_s_d_ARG1
[mips][msa] Implemented copy_[us].d intrinsic. This intrinsic is lowered into equivalent copy_s.w instructions during legalization. llvm-svn: 191518
2013-09-27 21:04:21 +08:00
%1 = tail call i64 @llvm.mips.copy.s.d(<2 x i64> %0, i32 1)
store i64 %1, i64* @llvm_mips_copy_s_d_RES
ret void
}
declare i64 @llvm.mips.copy.s.d(<2 x i64>, i32) nounwind
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY: llvm_mips_copy_s_d_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_d_ARG1)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_d_ARG1)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: copy_s.d [[RD:\$[0-9]+]], [[WS]][1]
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_d_RES)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS32-DAG: sw [[RD1]], 0([[RES]])
; MIPS32-DAG: sw [[RD2]], 4([[RES]])
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: sd [[RD]], 0([[RES]])
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY: .size llvm_mips_copy_s_d_test
[mips][msa] Implemented copy_[us].d intrinsic. This intrinsic is lowered into equivalent copy_s.w instructions during legalization. llvm-svn: 191518
2013-09-27 21:04:21 +08:00
;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
@llvm_mips_copy_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_copy_u_b_RES = global i32 0, align 16
define void @llvm_mips_copy_u_b_test() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_copy_u_b_ARG1
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
%1 = tail call i32 @llvm.mips.copy.u.b(<16 x i8> %0, i32 1)
store i32 %1, i32* @llvm_mips_copy_u_b_RES
ret void
}
declare i32 @llvm.mips.copy.u.b(<16 x i8>, i32) nounwind
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY: llvm_mips_copy_u_b_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_b_ARG1)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_b_ARG1)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])
; MIPS-ANY-DAG: copy_u.b [[RD:\$[0-9]+]], [[WS]][1]
; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_b_RES)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_b_RES)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
; MIPS-ANY: .size llvm_mips_copy_u_b_test
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
;
@llvm_mips_copy_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_copy_u_h_RES = global i32 0, align 16
define void @llvm_mips_copy_u_h_test() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_copy_u_h_ARG1
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
%1 = tail call i32 @llvm.mips.copy.u.h(<8 x i16> %0, i32 1)
store i32 %1, i32* @llvm_mips_copy_u_h_RES
ret void
}
declare i32 @llvm.mips.copy.u.h(<8 x i16>, i32) nounwind
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY: llvm_mips_copy_u_h_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_h_ARG1)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_h_ARG1)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])
; MIPS-ANY-DAG: copy_u.h [[RD:\$[0-9]+]], [[WS]][1]
; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_h_RES)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_h_RES)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
; MIPS-ANY: .size llvm_mips_copy_u_h_test
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
;
@llvm_mips_copy_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@llvm_mips_copy_u_w_RES = global i32 0, align 16
define void @llvm_mips_copy_u_w_test() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_copy_u_w_ARG1
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
%1 = tail call i32 @llvm.mips.copy.u.w(<4 x i32> %0, i32 1)
store i32 %1, i32* @llvm_mips_copy_u_w_RES
ret void
}
declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY: llvm_mips_copy_u_w_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_w_ARG1)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_ARG1)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
; MIPS-ANY-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1]
; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_w_RES)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_RES)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
; MIPS-ANY: .size llvm_mips_copy_u_w_test
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
;
[mips][msa] Implemented copy_[us].d intrinsic. This intrinsic is lowered into equivalent copy_s.w instructions during legalization. llvm-svn: 191518
2013-09-27 21:04:21 +08:00
@llvm_mips_copy_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
@llvm_mips_copy_u_d_RES = global i64 0, align 16
define void @llvm_mips_copy_u_d_test() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_copy_u_d_ARG1
[mips][msa] Implemented copy_[us].d intrinsic. This intrinsic is lowered into equivalent copy_s.w instructions during legalization. llvm-svn: 191518
2013-09-27 21:04:21 +08:00
%1 = tail call i64 @llvm.mips.copy.u.d(<2 x i64> %0, i32 1)
store i64 %1, i64* @llvm_mips_copy_u_d_RES
ret void
}
declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32) nounwind
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY: llvm_mips_copy_u_d_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_d_ARG1)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_ARG1)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: copy_u.d [[RD:\$[0-9]+]], [[WS]][1]
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_d_RES)
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_RES)
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS32-DAG: sw [[RD1]], 0([[RES]])
; MIPS32-DAG: sw [[RD2]], 4([[RES]])
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
; MIPS64-DAG: sd [[RD]], 0([[RES]])
[mips][msa] CHECK-DAG-ize MSA elm_copy.ll test. This update is a preparation for the addition of Mips64 MSA tests. No functional changes. llvm-svn: 200395
2014-01-29 21:51:34 +08:00
; MIPS-ANY: .size llvm_mips_copy_u_d_test
[mips][msa] Implemented copy_[us].d intrinsic. This intrinsic is lowered into equivalent copy_s.w instructions during legalization. llvm-svn: 191518
2013-09-27 21:04:21 +08:00
;