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llvm-project/llvm/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll

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This patch eanble register coalescing to coalesce the following: %vreg2<def> = MOVi32imm 1; GPR32:%vreg2 %W1<def> = COPY %vreg2; GPR32:%vreg2 into: %W1<def> = MOVi32imm 1 Patched by Lawrence Hu (lawrence@codeaurora.org) llvm-svn: 243033
2015-07-24 03:24:53 +08:00
; RUN: llc < %s | FileCheck %s
Fix CHECK directives that weren't checking. llvm-svn: 246485
2015-09-01 05:10:35 +08:00
; CHECK: orr w0, wzr, #0x1
; CHECK-NEXT: bl foo
; CHECK-NEXT: orr w0, wzr, #0x1
; CHECK-NEXT: bl foo
This patch eanble register coalescing to coalesce the following: %vreg2<def> = MOVi32imm 1; GPR32:%vreg2 %W1<def> = COPY %vreg2; GPR32:%vreg2 into: %W1<def> = MOVi32imm 1 Patched by Lawrence Hu (lawrence@codeaurora.org) llvm-svn: 243033
2015-07-24 03:24:53 +08:00
target triple = "aarch64--linux-android"
declare i32 @foo(i32)
; Function Attrs: nounwind uwtable
define i32 @main() {
entry:
%call = tail call i32 @foo(i32 1)
%call1 = tail call i32 @foo(i32 1)
ret i32 0
}