forked from OSchip/llvm-project
39 lines
1.3 KiB
LLVM
39 lines
1.3 KiB
LLVM
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; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
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; Test that the MinStart computation, which is based upon the length
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; of the chain edges, is computed correctly. A bug in the code allowed
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; two instuctions that have a chain edge to be scheduled more than II
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; instructions apart. In this test, if two stores appear before the
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; store, then that is a bug.
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; CHECK: r{{[0-9]+}} = memw([[REG0:r([0-9]+)]]+#12)
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; CHECK-NOT: r{{[0-9]+}} = memw([[REG0]]+#12)
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; CHECK: memw([[REG0]]+#12) = r{{[0-9]+}}
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%s.0 = type { i64, i32, i32, i32, i8* }
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@g0 = external global %s.0, align 8
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; Function Attrs: nounwind
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define void @f0() #0 {
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b0:
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%v0 = load i32, i32* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 1), align 8
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%v1 = ashr i32 %v0, 3
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b1, %b0
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%v2 = phi i32 [ %v5, %b1 ], [ 0, %b0 ]
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%v3 = load i8*, i8** getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 4), align 4
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%v4 = getelementptr inbounds i8, i8* %v3, i32 -1
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store i8* %v4, i8** getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 4), align 4
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store i8 0, i8* %v4, align 1
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%v5 = add nsw i32 %v2, 1
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%v6 = icmp eq i32 %v5, %v1
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br i1 %v6, label %b2, label %b1
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b2: ; preds = %b1, %b0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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