2016-08-16 22:29:24 +08:00
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; RUN: llc -march=hexagon -mcpu=hexagonv60 < %s
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; REQUIRES: asserts
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; Test that the pipeliner reuses an existing Phi when generating the epilog
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; block. In this case, the original loops has a Phi whose operand is another
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; Phi. When the loop is pipelined, the Phi that generates the operand value
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2018-01-24 13:04:35 +08:00
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; is used in two stages. This means the Phi for the second stage can
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2016-08-16 22:29:24 +08:00
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; be reused. The bug causes an assert due to an invalid virtual register error
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; in the live variable analysis.
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define void @test(i8* %a, i8* %b) #0 {
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entry:
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br label %for.body6.us.prol
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for.body6.us.prol:
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%i.065.us.prol = phi i32 [ 0, %entry ], [ %inc.us.prol, %for.body6.us.prol ]
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%im1.064.us.prol = phi i32 [ undef, %entry ], [ %i.065.us.prol, %for.body6.us.prol ]
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%prol.iter = phi i32 [ undef, %entry ], [ %prol.iter.sub, %for.body6.us.prol ]
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%arrayidx8.us.prol = getelementptr inbounds i8, i8* %b, i32 %im1.064.us.prol
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%0 = load i8, i8* %arrayidx8.us.prol, align 1
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%conv9.us.prol = sext i8 %0 to i32
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%add.us.prol = add nsw i32 %conv9.us.prol, 0
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%add12.us.prol = add nsw i32 %add.us.prol, 0
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%mul.us.prol = mul nsw i32 %add12.us.prol, 3
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%conv13.us.prol = trunc i32 %mul.us.prol to i8
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%arrayidx14.us.prol = getelementptr inbounds i8, i8* %a, i32 %i.065.us.prol
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store i8 %conv13.us.prol, i8* %arrayidx14.us.prol, align 1
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%inc.us.prol = add nuw nsw i32 %i.065.us.prol, 1
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%prol.iter.sub = add i32 %prol.iter, -1
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%prol.iter.cmp = icmp eq i32 %prol.iter.sub, 0
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br i1 %prol.iter.cmp, label %for.body6.us, label %for.body6.us.prol
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for.body6.us:
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%im2.063.us = phi i32 [ undef, %for.body6.us ], [ %im1.064.us.prol, %for.body6.us.prol ]
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%arrayidx10.us = getelementptr inbounds i8, i8* %b, i32 %im2.063.us
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%1 = load i8, i8* %arrayidx10.us, align 1
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%conv11.us = sext i8 %1 to i32
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%add12.us = add nsw i32 0, %conv11.us
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%mul.us = mul nsw i32 %add12.us, 3
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%conv13.us = trunc i32 %mul.us to i8
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store i8 %conv13.us, i8* undef, align 1
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br label %for.body6.us
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}
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