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llvm-project/clang/test/Headers/cpuid.c

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Fix bugs in cpuid.h. This commit makes two changes: - Remove the push and pop instructions that were saving and restoring %ebx before and after cpuid in 32-bit pic mode. We were doing this to ensure we don't lose the GOT address in pic register %ebx, but this isn't necessary because the GOT address is kept in a virtual register. - In 64-bit mode, preserve base register %rbx around cpuid. This fixes PR20311 and rdar://problem/17686779. llvm-svn: 218173
2014-09-20 09:31:09 +08:00
// RUN: %clang_cc1 %s -ffreestanding -triple x86_64-apple-darwin -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-64
// RUN: %clang_cc1 %s -ffreestanding -triple i386 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-32
#include <cpuid.h>
[clang] Add missing header guard in <cpuid.h> This header has long lacked a standard multiple inclusion guard like other headers have, for no apparent reason. The GCC header of the same name likewise lacks one up through release 10.1, but trunk GCC (release 11, and perhaps future 10.x) has fixed it (see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96238). Reviewed By: phosek Differential Revision: https://reviews.llvm.org/D91226
2020-11-11 10:56:59 +08:00
#include <cpuid.h> // Make sure multiple inclusion protection works.
Fix bugs in cpuid.h. This commit makes two changes: - Remove the push and pop instructions that were saving and restoring %ebx before and after cpuid in 32-bit pic mode. We were doing this to ensure we don't lose the GOT address in pic register %ebx, but this isn't necessary because the GOT address is kept in a virtual register. - In 64-bit mode, preserve base register %rbx around cpuid. This fixes PR20311 and rdar://problem/17686779. llvm-svn: 218173
2014-09-20 09:31:09 +08:00
// CHECK-64: {{.*}} call { i32, i32, i32, i32 } asm " xchgq %rbx,${1:q}\0A cpuid\0A xchgq %rbx,${1:q}", "={ax},=r,={cx},={dx},0,~{dirflag},~{fpsr},~{flags}"(i32 %{{[a-z0-9]+}})
// CHECK-64: {{.*}} call { i32, i32, i32, i32 } asm " xchgq %rbx,${1:q}\0A cpuid\0A xchgq %rbx,${1:q}", "={ax},=r,={cx},={dx},0,2,~{dirflag},~{fpsr},~{flags}"(i32 %{{[a-z0-9]+}}, i32 %{{[a-z0-9]+}})
// CHECK-32: {{.*}} call { i32, i32, i32, i32 } asm "cpuid", "={ax},={bx},={cx},={dx},0,~{dirflag},~{fpsr},~{flags}"(i32 %{{[a-z0-9]+}})
// CHECK-32: {{.*}} call { i32, i32, i32, i32 } asm "cpuid", "={ax},={bx},={cx},={dx},0,2,~{dirflag},~{fpsr},~{flags}"(i32 %{{[a-z0-9]+}}, i32 %{{[a-z0-9]+}})
unsigned eax0, ebx0, ecx0, edx0;
unsigned eax1, ebx1, ecx1, edx1;
void test_cpuid(unsigned level, unsigned count) {
__cpuid(level, eax1, ebx1, ecx1, edx1);
__cpuid_count(level, count, eax0, ebx0, ecx0, edx0);
}