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llvm-project/llvm/test/CodeGen/X86/2011-10-30-padd.ll

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Fix pr11266. On x86: (shl V, 1) -> add V,V Hardware support for vector-shift is sparse and in many cases we scalarize the result. Additionally, on sandybridge padd is faster than shl. llvm-svn: 143311
2011-10-30 21:24:22 +08:00
; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
;CHECK: addXX_test
;CHECK: padd
;CHECK: ret
define <16 x i8> @addXX_test(<16 x i8> %a) {
%b = add <16 x i8> %a, %a
ret <16 x i8> %b
}
;CHECK: instcombine_test
;CHECK: padd
;CHECK: ret
define <16 x i8> @instcombine_test(<16 x i8> %a) {
%b = shl <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %b
}