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llvm-project/llvm/test/CodeGen/SystemZ/cond-move-07.ll

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[SystemZ] Add support for new cpu architecture - arch13 This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Assembler/disassembler support for new instructions. - CodeGen for new instructions, including new LLVM intrinsics. - Scheduler description for the new processor. - Detection of arch13 as host processor. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365932
2019-07-13 02:13:16 +08:00
; Test SELFHR.
; See comments in asm-18.ll about testing high-word operations.
;
[SystemZ] Support z15 processor name The recently announced IBM z15 processor implements the architecture already supported as "arch13" in LLVM. This patch adds support for "z15" as an alternate architecture name for arch13. The patch also uses z15 in a number of places where we used arch13 as long as the official name was not yet announced. llvm-svn: 372435
2019-09-21 07:04:45 +08:00
; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z15 \
[SystemZ] Add support for new cpu architecture - arch13 This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Assembler/disassembler support for new instructions. - CodeGen for new instructions, including new LLVM intrinsics. - Scheduler description for the new processor. - Detection of arch13 as host processor. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365932
2019-07-13 02:13:16 +08:00
; RUN: -no-integrated-as | FileCheck %s
define void @f1(i32 %limit) {
; CHECK-LABEL: f1:
; CHECK-DAG: stepa [[REG1:%r[0-5]]]
; CHECK-DAG: stepb [[REG2:%r[0-5]]]
; CHECK-DAG: clfi %r2, 42
; CHECK: selfhrl [[REG3:%r[0-5]]], [[REG1]], [[REG2]]
; CHECK: stepc [[REG3]]
; CHECK: br %r14
%a = call i32 asm sideeffect "stepa $0", "=h"()
%b = call i32 asm sideeffect "stepb $0", "=h"()
%cond = icmp ult i32 %limit, 42
%res = select i1 %cond, i32 %a, i32 %b
call void asm sideeffect "stepc $0", "h"(i32 %res)
call void asm sideeffect "use $0", "h"(i32 %a)
call void asm sideeffect "use $0", "h"(i32 %b)
ret void
}
; Check that we also get SELFHR as a result of early if-conversion.
define void @f2(i32 %limit) {
; CHECK-LABEL: f2:
; CHECK-DAG: stepa [[REG1:%r[0-5]]]
; CHECK-DAG: stepb [[REG2:%r[0-5]]]
; CHECK-DAG: clfi %r2, 41
; CHECK: selfhrh [[REG3:%r[0-5]]], [[REG2]], [[REG1]]
; CHECK: stepc [[REG3]]
; CHECK: br %r14
entry:
%a = call i32 asm sideeffect "stepa $0", "=h"()
%b = call i32 asm sideeffect "stepb $0", "=h"()
%cond = icmp ult i32 %limit, 42
br i1 %cond, label %if.then, label %return
if.then:
br label %return
return:
%res = phi i32 [ %a, %if.then ], [ %b, %entry ]
call void asm sideeffect "stepc $0", "h"(i32 %res)
call void asm sideeffect "use $0", "h"(i32 %a)
call void asm sideeffect "use $0", "h"(i32 %b)
ret void
}
; Check that inverting the condition works as well.
define void @f3(i32 %limit) {
; CHECK-LABEL: f3:
; CHECK-DAG: stepa [[REG1:%r[0-5]]]
; CHECK-DAG: stepb [[REG2:%r[0-5]]]
; CHECK-DAG: clfi %r2, 41
; CHECK: selfhrh [[REG3:%r[0-5]]], [[REG1]], [[REG2]]
; CHECK: stepc [[REG3]]
; CHECK: br %r14
entry:
%a = call i32 asm sideeffect "stepa $0", "=h"()
%b = call i32 asm sideeffect "stepb $0", "=h"()
%cond = icmp ult i32 %limit, 42
br i1 %cond, label %if.then, label %return
if.then:
br label %return
return:
%res = phi i32 [ %b, %if.then ], [ %a, %entry ]
call void asm sideeffect "stepc $0", "h"(i32 %res)
call void asm sideeffect "use $0", "h"(i32 %a)
call void asm sideeffect "use $0", "h"(i32 %b)
ret void
}