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llvm-project/llvm/test/CodeGen/BPF/mem_offset_be.ll

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[bpf] add bigendian support to disassembler . swap 4-bit register encoding, 16-bit offset and 32-bit imm to support big endian archs . add a test Reported-by: David S. Miller <davem@davemloft.net> Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 301653
2017-04-29 00:51:01 +08:00
; RUN: llc -march=bpfeb -show-mc-encoding < %s | FileCheck %s
; Function Attrs: nounwind
define i32 @bpf_prog1(i8* nocapture readnone) local_unnamed_addr #0 {
bpf: add " ll" in the LD_IMM64 asmstring This partially revert previous fix in commit f5858045aa0b ("bpf: proper print imm64 expression in inst printer"). In that commit, the original suffix "ll" is removed from LD_IMM64 asmstring. In the customer print method, the "ll" suffix is printed if the rhs is an immediate. For example, "r2 = 5ll" => "r2 = 5ll", and "r3 = varll" => "r3 = var". This has an issue though for assembler. Since assembler relies on asmstring to do pattern matching, it will not be able to distiguish between "mov r2, 5" and "ld_imm64 r2, 5" since both asmstring is "r2 = 5". In such cases, the assembler uses 64bit load for all "r = <val>" asm insts. This patch adds back " ll" suffix for ld_imm64 with one additional space for "#reg = #global_var" case. Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 312978
2017-09-12 07:43:35 +08:00
; CHECK: r1 = 590618314553 ll # encoding: [0x18,0x10,0x00,0x00,0x83,0x98,0x47,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x89]
[bpf] add bigendian support to disassembler . swap 4-bit register encoding, 16-bit offset and 32-bit imm to support big endian archs . add a test Reported-by: David S. Miller <davem@davemloft.net> Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 301653
2017-04-29 00:51:01 +08:00
; CHECK: r1 += -1879113726 # encoding: [0x07,0x10,0x00,0x00,0x8f,0xff,0x00,0x02]
; CHECK: r0 = *(u64 *)(r1 + 0) # encoding: [0x79,0x01,0x00,0x00,0x00,0x00,0x00,0x00]
%2 = alloca i64, align 8
%3 = bitcast i64* %2 to i8*
store volatile i64 590618314553, i64* %2, align 8
%4 = load volatile i64, i64* %2, align 8
%5 = add i64 %4, -1879113726
%6 = inttoptr i64 %5 to i64*
%7 = load i64, i64* %6, align 8
%8 = trunc i64 %7 to i32
ret i32 %8
}