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llvm-project/llvm/test/MC/X86/x86-64.s

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fix the encoding of sldt GR16 to have the 0x66 prefix, and add sldt GR32, which isn't documented in the intel manual but which gas accepts. Part of rdar://8418316 llvm-svn: 113938
2010-09-15 12:45:10 +08:00
// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s > %t 2> %t.err
MC/X86: Warn on scale factors > 1 without index register, instead of erroring, for 'as' compatibility. llvm-svn: 111945
2010-08-25 03:13:38 +08:00
// RUN: FileCheck < %t %s
// RUN: FileCheck --check-prefix=CHECK-STDERR < %t.err %s
Add this test back, the check pattern was too strict. llvm-svn: 77662
2009-07-31 11:11:49 +08:00
Recognize monitor/mwait with explicit register arguments llvm-svn: 125805
2011-02-18 08:48:11 +08:00
monitor
// CHECK: monitor
// CHECK: encoding: [0x0f,0x01,0xc8]
monitor %rax, %rcx, %rdx
// CHECK: monitor
// CHECK: encoding: [0x0f,0x01,0xc8]
mwait
// CHECK: mwait
// CHECK: encoding: [0x0f,0x01,0xc9]
mwait %rax, %rcx
// CHECK: mwait
// CHECK: encoding: [0x0f,0x01,0xc9]
merge and clean up tests. llvm-svn: 115177
2010-10-01 01:24:05 +08:00
// Suffix inference:
// CHECK: addl $0, %eax
add $0, %eax
// CHECK: addb $255, %al
add $0xFF, %al
// CHECK: orq %rax, %rdx
or %rax, %rdx
// CHECK: shlq $3, %rax
shl $3, %rax
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: subb %al, %al
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. llvm-svn: 77728
2009-08-01 04:53:16 +08:00
subb %al, %al
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: addl $24, %eax
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. llvm-svn: 77728
2009-08-01 04:53:16 +08:00
addl $24, %eax
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: movl %eax, 10(%ebp)
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. llvm-svn: 77728
2009-08-01 04:53:16 +08:00
movl %eax, 10(%ebp)
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: movl %eax, 10(%ebp,%ebx)
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. llvm-svn: 77728
2009-08-01 04:53:16 +08:00
movl %eax, 10(%ebp, %ebx)
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: movl %eax, 10(%ebp,%ebx,4)
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. llvm-svn: 77728
2009-08-01 04:53:16 +08:00
movl %eax, 10(%ebp, %ebx, 4)
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: movl %eax, 10(,%ebx,4)
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. llvm-svn: 77728
2009-08-01 04:53:16 +08:00
movl %eax, 10(, %ebx, 4)
MC/X86 AsmParser: Handle absolute memory operands correctly. We were doing something totally broken and parsing them as immediates, but the .td file also had the wrong match class so things sortof worked. Except, that is, that we would parse movl $0, %eax as movl 0, %eax Feel free to guess how well that worked. llvm-svn: 94869
2010-01-30 09:02:48 +08:00
// CHECK: movl 0, %eax
movl 0, %eax
// CHECK: movl $0, %eax
movl $0, %eax
Mark EH_RETURN64 as CodeGenOnly. llvm-svn: 94205
2010-01-23 04:16:37 +08:00
// CHECK: ret
ret
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 15:20:21 +08:00
// FIXME: Check that this matches SUB32ri8
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: subl $1, %eax
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 15:20:21 +08:00
subl $1, %eax
// FIXME: Check that this matches SUB32ri8
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: subl $-1, %eax
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 15:20:21 +08:00
subl $-1, %eax
// FIXME: Check that this matches SUB32ri
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: subl $256, %eax
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 15:20:21 +08:00
subl $256, %eax
llvm-mc/AsmParser: Disambiguate i64i8imm. llvm-svn: 78598
2009-08-11 05:06:41 +08:00
// FIXME: Check that this matches XOR64ri8
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: xorq $1, %rax
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands. - This drops us to 123 ambiguous instructions (previously ~500) on X86. llvm-svn: 78636
2009-08-11 10:59:53 +08:00
xorq $1, %rax
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 15:20:21 +08:00
llvm-mc/AsmParser: Disambiguate i64i8imm. llvm-svn: 78598
2009-08-11 05:06:41 +08:00
// FIXME: Check that this matches XOR64ri32
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: xorq $256, %rax
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands. - This drops us to 123 ambiguous instructions (previously ~500) on X86. llvm-svn: 78636
2009-08-11 10:59:53 +08:00
xorq $256, %rax
// FIXME: Check that this matches SUB8rr
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: subb %al, %bl
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands. - This drops us to 123 ambiguous instructions (previously ~500) on X86. llvm-svn: 78636
2009-08-11 10:59:53 +08:00
subb %al, %bl
// FIXME: Check that this matches SUB16rr
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: subw %ax, %bx
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands. - This drops us to 123 ambiguous instructions (previously ~500) on X86. llvm-svn: 78636
2009-08-11 10:59:53 +08:00
subw %ax, %bx
// FIXME: Check that this matches SUB32rr
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: subl %eax, %ebx
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands. - This drops us to 123 ambiguous instructions (previously ~500) on X86. llvm-svn: 78636
2009-08-11 10:59:53 +08:00
subl %eax, %ebx
llvm-mc/X86: Parse '*' correctly (in the way the matcher expects). llvm-svn: 78642
2009-08-11 13:00:25 +08:00
// FIXME: Check that this matches the correct instruction.
X86-64: Mark WINCALL and more tail call instructions as code gen only. llvm-svn: 108685
2010-07-19 15:21:07 +08:00
// CHECK: callq *%rax
llvm-mc/X86: Parse '*' correctly (in the way the matcher expects). llvm-svn: 78642
2009-08-11 13:00:25 +08:00
call *%rax
llvm-mc/AsmParser: Match hard coded registers (e.g. 'shldl %cl, %eax, %eax') We now match all of 403.gcc (as emitted by clang). :) llvm-svn: 78750
2009-08-12 07:23:44 +08:00
// FIXME: Check that this matches the correct instruction.
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) llvm-svn: 78986
2009-08-14 11:48:55 +08:00
// CHECK: shldl %cl, %eax, %ebx
llvm-mc/AsmParser: Match hard coded registers (e.g. 'shldl %cl, %eax, %eax') We now match all of 403.gcc (as emitted by clang). :) llvm-svn: 78750
2009-08-12 07:23:44 +08:00
shldl %cl, %eax, %ebx
AsmParser/X86: Add temporary hack to allow parsing "sal". Eventually we need some mechanism for specifying alternative syntaxes, but I'm not sure what form that should take yet. llvm-svn: 95158
2010-02-03 07:46:47 +08:00
// CHECK: shll $2, %eax
shll $2, %eax
// CHECK: shll $2, %eax
sall $2, %eax
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
// CHECK: rep
// CHECK: insb
rep;insb
// CHECK: rep
// CHECK: outsb
rep;outsb
// CHECK: rep
// CHECK: movsb
rep;movsb
fix rdar://8470918 - llvm-mc can't assemble smovl llvm-svn: 114819
2010-09-27 15:11:53 +08:00
// rdar://8470918
smovb // CHECK: movsb
smovw // CHECK: movsw
smovl // CHECK: movsl
smovq // CHECK: movsq
fix rdar://8456361 - llvm-mc rejects 'rep movsd' llvm-svn: 114526
2010-09-22 11:50:32 +08:00
// rdar://8456361
// CHECK: rep
// CHECK: movsl
rep movsd
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
// CHECK: rep
// CHECK: lodsb
rep;lodsb
// CHECK: rep
// CHECK: stosb
rep;stosb
// NOTE: repz and repe have the same opcode as rep
// CHECK: rep
// CHECK: cmpsb
repz;cmpsb
// NOTE: repnz has the same opcode as repne
// CHECK: repne
// CHECK: cmpsb
repnz;cmpsb
// NOTE: repe and repz have the same opcode as rep
// CHECK: rep
// CHECK: scasb
repe;scasb
// CHECK: repne
// CHECK: scasb
repne;scasb
// CHECK: lock
MC/X86: Push immediate operands as immediates not expressions when possible. llvm-svn: 96055
2010-02-13 08:17:21 +08:00
// CHECK: cmpxchgb %al, (%ebx)
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
lock;cmpxchgb %al, 0(%ebx)
// CHECK: cs
MC/X86: Push immediate operands as immediates not expressions when possible. llvm-svn: 96055
2010-02-13 08:17:21 +08:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
cs;movb 0(%eax), %al
// CHECK: ss
MC/X86: Push immediate operands as immediates not expressions when possible. llvm-svn: 96055
2010-02-13 08:17:21 +08:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
ss;movb 0(%eax), %al
// CHECK: ds
MC/X86: Push immediate operands as immediates not expressions when possible. llvm-svn: 96055
2010-02-13 08:17:21 +08:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
ds;movb 0(%eax), %al
// CHECK: es
MC/X86: Push immediate operands as immediates not expressions when possible. llvm-svn: 96055
2010-02-13 08:17:21 +08:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
es;movb 0(%eax), %al
// CHECK: fs
MC/X86: Push immediate operands as immediates not expressions when possible. llvm-svn: 96055
2010-02-13 08:17:21 +08:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
fs;movb 0(%eax), %al
// CHECK: gs
MC/X86: Push immediate operands as immediates not expressions when possible. llvm-svn: 96055
2010-02-13 08:17:21 +08:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
gs;movb 0(%eax), %al
Implement x86 asm parsing support for %st and %st(4) llvm-svn: 95634
2010-02-09 08:49:22 +08:00
// CHECK: fadd %st(0)
// CHECK: fadd %st(1)
// CHECK: fadd %st(7)
fadd %st(0)
fadd %st(1)
fadd %st(7)
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. - This fixes "leal 0, %eax", for example. llvm-svn: 103205
2010-05-07 06:39:14 +08:00
// CHECK: leal 0, %eax
leal 0, %eax
fix rdar://7986634 - match instruction opcodes case insensitively. llvm-svn: 104183
2010-05-20 07:34:33 +08:00
// rdar://7986634 - Insensitivity on opcodes.
// CHECK: int3
INT3
MC/X86: Warn on scale factors > 1 without index register, instead of erroring, for 'as' compatibility. llvm-svn: 111945
2010-08-25 03:13:38 +08:00
// Allow scale factor without index register.
// CHECK: movaps %xmm3, (%esi)
// CHECK-STDERR: warning: scale factor without index register is ignored
movaps %xmm3, (%esi, 2)
MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends. llvm-svn: 111947
2010-08-25 03:24:18 +08:00
// CHECK: imull $12, %eax, %eax
imul $12, %eax
MC/X86: Tweak imul recognition, previous hack only applies for the imul form taking immediates. llvm-svn: 111950
2010-08-25 03:37:56 +08:00
// CHECK: imull %ecx, %eax
imull %ecx, %eax
fix the operand constraints of the immediate form of in/out, allowing unsigned 8-bit operands. This fixes rdar://8208481 llvm-svn: 113182
2010-09-07 07:29:05 +08:00
// rdar://8208481
// CHECK: outb %al, $161
outb %al, $161
// CHECK: outw %ax, $128
outw %ax, $128
// CHECK: inb $161, %al
inb $161, %al
fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)" llvm-svn: 113184
2010-09-07 07:40:56 +08:00
// rdar://8017621
// CHECK: pushq $1
push $1
"sldt <mem>" is ambiguous in 64-bit mode, but should always be disambiguated as sldtw. sldtw and sldtq with a mem operands have the same effect, but sldtw is more compact. Force it to sldtw, resolving rdar://8017530 llvm-svn: 113186
2010-09-07 07:51:44 +08:00
// rdar://8017530
// CHECK: sldtw 4
sldt 4
add missing cmov aliases, this resolves rdar://8208499 llvm-svn: 113189
2010-09-07 08:05:45 +08:00
// rdar://8208499
// CHECK: cmovnew %bx, %ax
cmovnz %bx, %ax
// CHECK: cmovneq %rbx, %rax
cmovnzq %rbx, %rax
implement rdar://8407928 - support for in/out with a missing "a" register. llvm-svn: 113689
2010-09-12 00:32:12 +08:00
// rdar://8407928
// CHECK: inb $127, %al
// CHECK: inw %dx, %ax
// CHECK: outb %al, $127
// CHECK: outw %ax, %dx
// CHECK: inl %dx, %eax
inb $0x7f
inw %dx
outb $0x7f
outw %dx
inl %dx
add a terrible hack to allow out with dx is parens, a gas bug. This fixes PR8114 llvm-svn: 113894
2010-09-15 07:34:29 +08:00
// PR8114
// CHECK: outb %al, %dx
// CHECK: outw %ax, %dx
// CHECK: outl %eax, %dx
out %al, (%dx)
out %ax, (%dx)
outl %eax, (%dx)
add a bunch of aliases for fp operations with no operand, rdar://8431422 llvm-svn: 113929
2010-09-15 12:04:33 +08:00
// rdar://8431422
// CHECK: fxch %st(1)
// CHECK: fucom %st(1)
// CHECK: fucomp %st(1)
// CHECK: faddp %st(1)
// CHECK: faddp %st(0)
// CHECK: fsubp %st(1)
// CHECK: fsubrp %st(1)
// CHECK: fmulp %st(1)
// CHECK: fdivp %st(1)
// CHECK: fdivrp %st(1)
fxch
fucom
fucomp
faddp
faddp %st
fsubp
fsubrp
fmulp
fdivp
fdivrp
add some aliases for f[u]comi, part of rdar://8431422 llvm-svn: 113930
2010-09-15 12:08:38 +08:00
change the fp comparison instructions to not have %st0 explicitly listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
2010-11-07 04:55:09 +08:00
// CHECK: fcomi %st(1)
// CHECK: fcomi %st(2)
// CHECK: fucomi %st(1)
// CHECK: fucomi %st(2)
// CHECK: fucomi %st(2)
add some aliases for f[u]comi, part of rdar://8431422 llvm-svn: 113930
2010-09-15 12:08:38 +08:00
fcomi
fcomi %st(2)
fucomi
fucomi %st(2)
fucomi %st(2), %st
add various broken forms of fnstsw. I didn't add the %rax version because it adds a prefix and makes even less sense than the other broken forms. This wraps up rdar://8431422 llvm-svn: 113932
2010-09-15 12:15:16 +08:00
// CHECK: fnstsw %ax
// CHECK: fnstsw %ax
// CHECK: fnstsw %ax
// CHECK: fnstsw %ax
fnstsw
fnstsw %ax
fnstsw %eax
fnstsw %al
fix rdar://8431880 - rcl/rcr with no shift amount not recognized llvm-svn: 113936
2010-09-15 12:33:27 +08:00
// rdar://8431880
rework the rotate-by-1 instructions to be defined like the shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. llvm-svn: 118355
2010-11-07 05:23:40 +08:00
// CHECK: rclb %bl
// CHECK: rcll 3735928559(%ebx,%ecx,8)
// CHECK: rcrl %ecx
// CHECK: rcrl 305419896
fix rdar://8431880 - rcl/rcr with no shift amount not recognized llvm-svn: 113936
2010-09-15 12:33:27 +08:00
rcl %bl
rcll 0xdeadbeef(%ebx,%ecx,8)
rcr %ecx
rcrl 0x12345678
implement aliases for shld/shrd, part of rdar://8418316 llvm-svn: 113937
2010-09-15 12:37:18 +08:00
rework the rotate-by-1 instructions to be defined like the shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. llvm-svn: 118355
2010-11-07 05:23:40 +08:00
rclb %bl // CHECK: rclb %bl # encoding: [0xd0,0xd3]
rclb $1, %bl // CHECK: rclb %bl # encoding: [0xd0,0xd3]
rclb $2, %bl // CHECK: rclb $2, %bl # encoding: [0xc0,0xd3,0x02]
implement aliases for shld/shrd, part of rdar://8418316 llvm-svn: 113937
2010-09-15 12:37:18 +08:00
// rdar://8418316
// CHECK: shldw $1, %bx, %bx
// CHECK: shldw $1, %bx, %bx
// CHECK: shrdw $1, %bx, %bx
// CHECK: shrdw $1, %bx, %bx
shld %bx,%bx
shld $1, %bx,%bx
shrd %bx,%bx
shrd $1, %bx,%bx
fix the encoding of sldt GR16 to have the 0x66 prefix, and add sldt GR32, which isn't documented in the intel manual but which gas accepts. Part of rdar://8418316 llvm-svn: 113938
2010-09-15 12:45:10 +08:00
// CHECK: sldtl %ecx
// CHECK: encoding: [0x0f,0x00,0xc1]
// CHECK: sldtw %cx
// CHECK: encoding: [0x66,0x0f,0x00,0xc1]
sldt %ecx
sldt %cx
Disambiguate lcall/ljmp to the 32-bit version. This happens even in 64-bit mode apparently. llvm-svn: 113945
2010-09-15 13:14:54 +08:00
// CHECK: lcalll *3135175374
// CHECK: ljmpl *3135175374
lcall *0xbadeface
ljmp *0xbadeface
fix rdar://8444631 - encoder crash on 'enter' What a weird instruction. llvm-svn: 114190
2010-09-18 02:02:29 +08:00
// rdar://8444631
// CHECK: enter $31438, $0
// CHECK: encoding: [0xc8,0xce,0x7a,0x00]
// CHECK: enter $31438, $1
// CHECK: encoding: [0xc8,0xce,0x7a,0x01]
// CHECK: enter $31438, $127
// CHECK: encoding: [0xc8,0xce,0x7a,0x7f]
enter $0x7ace,$0
enter $0x7ace,$1
enter $0x7ace,$0x7f
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp' -This line, and those below, will be ignored-- M test/MC/AsmParser/X86/x86_instructions.s M lib/Target/X86/AsmParser/X86AsmParser.cpp llvm-svn: 114527
2010-09-22 12:04:03 +08:00
Fix rdar://8456364 - llvm-mc rejects '%CS' llvm-svn: 114528
2010-09-22 12:11:10 +08:00
// rdar://8456364
// CHECK: movw %cs, %ax
mov %CS, %ax
add the missing aliases for fp stack cmovs, rdar://8456391 llvm-svn: 114531
2010-09-22 12:56:20 +08:00
// rdar://8456391
fcmovb %st(1), %st(0) // CHECK: fcmovb %st(1), %st(0)
fcmove %st(1), %st(0) // CHECK: fcmove %st(1), %st(0)
fcmovbe %st(1), %st(0) // CHECK: fcmovbe %st(1), %st(0)
fcmovu %st(1), %st(0) // CHECK: fcmovu %st(1), %st(0)
fcmovnb %st(1), %st(0) // CHECK: fcmovnb %st(1), %st(0)
fcmovne %st(1), %st(0) // CHECK: fcmovne %st(1), %st(0)
fcmovnbe %st(1), %st(0) // CHECK: fcmovnbe %st(1), %st(0)
fcmovnu %st(1), %st(0) // CHECK: fcmovnu %st(1), %st(0)
fcmovnae %st(1), %st(0) // CHECK: fcmovb %st(1), %st(0)
fcmovna %st(1), %st(0) // CHECK: fcmovbe %st(1), %st(0)
fcmovae %st(1), %st(0) // CHECK: fcmovnb %st(1), %st(0)
fcmova %st(1), %st(0) // CHECK: fcmovnbe %st(1), %st(0)
fix rdar://8456417 - llvm-mc can't do basic math llvm-svn: 114532
2010-09-22 13:05:16 +08:00
// rdar://8456417
.byte 88 + 1 & 15 // CHECK: .byte 9
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8" Teaching the code generator about CR8-15, how to rex them up, etc. llvm-svn: 114533
2010-09-22 13:29:50 +08:00
// rdar://8456412
mov %rdx, %cr0
// CHECK: movq %rdx, %cr0
// CHECK: encoding: [0x0f,0x22,0xc2]
mov %rdx, %cr4
// CHECK: movq %rdx, %cr4
// CHECK: encoding: [0x0f,0x22,0xe2]
mov %rdx, %cr8
// CHECK: movq %rdx, %cr8
// CHECK: encoding: [0x44,0x0f,0x22,0xc2]
mov %rdx, %cr15
// CHECK: movq %rdx, %cr15
// CHECK: encoding: [0x44,0x0f,0x22,0xfa]
fix rdar://8456371 - Handle commutable instructions written backward. llvm-svn: 114536
2010-09-22 14:26:39 +08:00
// rdar://8456371 - Handle commutable instructions written backward.
// CHECK: faddp %st(1)
// CHECK: fmulp %st(2)
faddp %st, %st(1)
fmulp %st, %st(2)
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands. My previous fix for rdar://8456371 should only apply to fmulp/faddp, not to fmul/fadd. Instruction set orthogonality is overrated or something. llvm-svn: 114818
2010-09-27 15:08:21 +08:00
// rdar://8468087 - Encode these accurately, they are not synonyms.
// CHECK: fmul %st(0), %st(1)
// CHECK: encoding: [0xdc,0xc9]
// CHECK: fmul %st(1)
// CHECK: encoding: [0xd8,0xc9]
fmul %st, %st(1)
fmul %st(1), %st
// CHECK: fadd %st(0), %st(1)
// CHECK: encoding: [0xdc,0xc1]
// CHECK: fadd %st(1)
// CHECK: encoding: [0xd8,0xc1]
fadd %st, %st(1)
fadd %st(1), %st
implement support for 'clr' alias. This is part of rdar://8416805, but balrog was wanting it on irc. llvm-svn: 114809
2010-09-27 12:23:03 +08:00
// rdar://8416805
// CHECK: xorb %al, %al
// CHECK: encoding: [0x30,0xc0]
// CHECK: xorw %di, %di
// CHECK: encoding: [0x66,0x31,0xff]
// CHECK: xorl %esi, %esi
// CHECK: encoding: [0x31,0xf6]
// CHECK: xorq %rsi, %rsi
// CHECK: encoding: [0x48,0x31,0xf6]
clrb %al
clr %di
clr %esi
clr %rsi
add a couple more aliases, rdar://8456378 llvm-svn: 114821
2010-09-27 15:21:41 +08:00
// rdar://8456378
cltq // CHECK: cltq
cdqe // CHECK: cltq
cwde // CHECK: cwtl
cwtl // CHECK: cwtl
fix rdar://8456371 - Handle commutable instructions written backward. llvm-svn: 114536
2010-09-22 14:26:39 +08:00
yet more aliases. llvm-svn: 114822
2010-09-27 15:24:57 +08:00
// rdar://8416805
cbw // CHECK: cbtw
cwd // CHECK: cwtd
cdq // CHECK: cltd
implement rdar://8456378 and PR7557 - support for the fstsw, an instruction that requires a WHOLE NEW wonderful kind of alias. llvm-svn: 115015
2010-09-29 09:50:45 +08:00
// rdar://8456378 and PR7557 - fstsw
fstsw %ax
// CHECK: wait
// CHECK: fnstsw %ax
fstsw (%rax)
// CHECK: wait
Reverting r117031 to cleanup valgrind errors. It doesn't look like anything is wrong with the checkin, but the new test cases expose a mem bug in AsmParser. llvm-svn: 117087
2010-10-22 11:58:29 +08:00
// CHECK: fnstsw (%rax)
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes. llvm-svn: 115017
2010-09-29 10:24:57 +08:00
add support for fstcw, PR8259 llvm-svn: 115154
2010-10-01 00:39:29 +08:00
// PR8259
fstcw (%rsp)
// CHECK: wait
Reverting r117031 to cleanup valgrind errors. It doesn't look like anything is wrong with the checkin, but the new test cases expose a mem bug in AsmParser. llvm-svn: 117087
2010-10-22 11:58:29 +08:00
// CHECK: fnstcw (%rsp)
add support for fstcw, PR8259 llvm-svn: 115154
2010-10-01 00:39:29 +08:00
implement support for finit, PR8258 llvm-svn: 115156
2010-10-01 00:42:53 +08:00
// PR8259
fstcw (%rsp)
// CHECK: wait
Reverting r117031 to cleanup valgrind errors. It doesn't look like anything is wrong with the checkin, but the new test cases expose a mem bug in AsmParser. llvm-svn: 117087
2010-10-22 11:58:29 +08:00
// CHECK: fnstcw (%rsp)
implement support for finit, PR8258 llvm-svn: 115156
2010-10-01 00:42:53 +08:00
// PR8258
finit
// CHECK: wait
// CHECK: fninit
preemptively add the rest of the non-n fpstack instructions. llvm-svn: 115168
2010-10-01 01:11:29 +08:00
fsave 32493
// CHECK: wait
// CHECK: fnsave 32493
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes. llvm-svn: 115017
2010-09-29 10:24:57 +08:00
// rdar://8456382 - cvtsd2si support.
cvtsd2si %xmm1, %rax
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382 llvm-svn: 115027
2010-09-29 12:55:40 +08:00
// CHECK: cvtsd2siq %xmm1, %rax
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes. llvm-svn: 115017
2010-09-29 10:24:57 +08:00
// CHECK: encoding: [0xf2,0x48,0x0f,0x2d,0xc1]
cvtsd2si %xmm1, %eax
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382 llvm-svn: 115027
2010-09-29 12:55:40 +08:00
// CHECK: cvtsd2sil %xmm1, %eax
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes. llvm-svn: 115017
2010-09-29 10:24:57 +08:00
// CHECK: encoding: [0xf2,0x0f,0x2d,0xc1]
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382 llvm-svn: 115027
2010-09-29 12:55:40 +08:00
cvtsd2siq %xmm0, %rax // CHECK: cvtsd2siq %xmm0, %rax
cvtsd2sil %xmm0, %eax // CHECK: cvtsd2sil %xmm0, %eax
cvtsd2si %xmm0, %rax // CHECK: cvtsd2siq %xmm0, %rax
add asmparser support for cvttpd2dq by removing some Int_ prefixes. Clean up cvttps2dq by removing some redundant implementations of the same instruction. rdar://8456382 llvm-svn: 115018
2010-09-29 10:36:32 +08:00
cvttpd2dq %xmm1, %xmm0 // CHECK: cvttpd2dq %xmm1, %xmm0
cvttpd2dq (%rax), %xmm0 // CHECK: cvttpd2dq (%rax), %xmm0
cvttps2dq %xmm1, %xmm0 // CHECK: cvttps2dq %xmm1, %xmm0
cvttps2dq (%rax), %xmm0 // CHECK: cvttps2dq (%rax), %xmm0
add basic avx support to the disassembler, also teach it about ssmem/sdmem operands. With this done, we can remove the _Int suffixes from the round instructions without the disassembler blowing up. This allows the assembler to support them, implementing rdar://8456376 - llvm-mc rejects 'roundss' llvm-svn: 115019
2010-09-29 10:57:56 +08:00
// rdar://8456376 - llvm-mc rejects 'roundss'
roundss $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x0a,0xc0,0x0e]
roundps $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x08,0xc0,0x0e]
roundsd $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x0b,0xc0,0x0e]
roundpd $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x09,0xc0,0x0e]
implement support for 32-bit address operands in 64-bit mode, which are defined to emit the 0x67 prefix byte. rdar://8482675 llvm-svn: 115021
2010-09-29 11:33:25 +08:00
// rdar://8482675 - 32-bit mem operand support in 64-bit mode (0x67 prefix)
leal 8(%eax), %esi
// CHECK: leal 8(%eax), %esi
// CHECK: encoding: [0x67,0x8d,0x70,0x08]
leaq 8(%eax), %rsi
// CHECK: leaq 8(%eax), %rsi
// CHECK: encoding: [0x67,0x48,0x8d,0x70,0x08]
leaq 8(%rax), %rsi
// CHECK: leaq 8(%rax), %rsi
// CHECK: encoding: [0x48,0x8d,0x70,0x08]
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same order as cctools for diffability. llvm-svn: 115022
2010-09-29 11:43:43 +08:00
cvttpd2dq 0xdeadbeef(%ebx,%ecx,8),%xmm5
// CHECK: cvttpd2dq 3735928559(%ebx,%ecx,8), %xmm5
// CHECK: encoding: [0x67,0x66,0x0f,0xe6,0xac,0xcb,0xef,0xbe,0xad,0xde]
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd' llvm-svn: 115029
2010-09-29 13:05:03 +08:00
// rdar://8490728 - llvm-mc rejects 'movmskpd'
movmskpd %xmm6, %rax
// CHECK: movmskpd %xmm6, %rax
// CHECK: encoding: [0x66,0x48,0x0f,0x50,0xc6]
movmskpd %xmm6, %eax
// CHECK: movmskpd %xmm6, %eax
// CHECK: encoding: [0x66,0x0f,0x50,0xc6]
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions. llvm-svn: 115061
2010-09-30 02:39:16 +08:00
// rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
fdivrp %st(0), %st(1) // CHECK: encoding: [0xde,0xf9]
fdivrp %st(1), %st(0) // CHECK: encoding: [0xde,0xf9]
fsubrp %ST(0), %ST(1) // CHECK: encoding: [0xde,0xe9]
fsubrp %ST(1), %ST(0) // CHECK: encoding: [0xde,0xe9]
Add another non-commutable instruction that gas accepts commuted forms for. Fixes PR8861. llvm-svn: 122641
2010-12-31 06:10:49 +08:00
// also PR8861
fdivp %st(0), %st(1) // CHECK: encoding: [0xde,0xf1]
fdivp %st(1), %st(0) // CHECK: encoding: [0xde,0xf1]
add support for fstcw, PR8259 llvm-svn: 115154
2010-10-01 00:39:29 +08:00
merge two tests. llvm-svn: 115170
2010-10-01 01:14:30 +08:00
movl foo(%rip), %eax
// CHECK: movl foo(%rip), %eax
// CHECK: encoding: [0x8b,0x05,A,A,A,A]
// CHECK: fixup A - offset: 2, value: foo-4, kind: reloc_riprel_4byte
movb $12, foo(%rip)
// CHECK: movb $12, foo(%rip)
// CHECK: encoding: [0xc6,0x05,A,A,A,A,0x0c]
// CHECK: fixup A - offset: 2, value: foo-5, kind: reloc_riprel_4byte
movw $12, foo(%rip)
// CHECK: movw $12, foo(%rip)
// CHECK: encoding: [0x66,0xc7,0x05,A,A,A,A,0x0c,0x00]
// CHECK: fixup A - offset: 3, value: foo-6, kind: reloc_riprel_4byte
movl $12, foo(%rip)
// CHECK: movl $12, foo(%rip)
// CHECK: encoding: [0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00]
// CHECK: fixup A - offset: 2, value: foo-8, kind: reloc_riprel_4byte
movq $12, foo(%rip)
// CHECK: movq $12, foo(%rip)
// CHECK: encoding: [0x48,0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00]
// CHECK: fixup A - offset: 3, value: foo-8, kind: reloc_riprel_4byte
// CHECK: addq $-424, %rax
// CHECK: encoding: [0x48,0x05,0x58,0xfe,0xff,0xff]
addq $-424, %rax
// CHECK: movq _foo@GOTPCREL(%rip), %rax
// CHECK: encoding: [0x48,0x8b,0x05,A,A,A,A]
// CHECK: fixup A - offset: 3, value: _foo@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
movq _foo@GOTPCREL(%rip), %rax
// CHECK: movq _foo@GOTPCREL(%rip), %r14
// CHECK: encoding: [0x4c,0x8b,0x35,A,A,A,A]
// CHECK: fixup A - offset: 3, value: _foo@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
movq _foo@GOTPCREL(%rip), %r14
// CHECK: movq (%r13,%rax,8), %r13
// CHECK: encoding: [0x4d,0x8b,0x6c,0xc5,0x00]
movq 0x00(%r13,%rax,8),%r13
// CHECK: testq %rax, %rbx
// CHECK: encoding: [0x48,0x85,0xd8]
testq %rax, %rbx
// CHECK: cmpq %rbx, %r14
// CHECK: encoding: [0x49,0x39,0xde]
cmpq %rbx, %r14
// rdar://7947167
movsq
// CHECK: movsq
// CHECK: encoding: [0x48,0xa5]
movsl
// CHECK: movsl
// CHECK: encoding: [0xa5]
stosq
// CHECK: stosq
// CHECK: encoding: [0x48,0xab]
stosl
// CHECK: stosl
// CHECK: encoding: [0xab]
// Not moffset forms of moves, they are x86-32 only! rdar://7947184
movb 0, %al // CHECK: movb 0, %al # encoding: [0x8a,0x04,0x25,0x00,0x00,0x00,0x00]
movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
// CHECK: pushfq # encoding: [0x9c]
pushf
// CHECK: pushfq # encoding: [0x9c]
pushfq
// CHECK: popfq # encoding: [0x9d]
popf
// CHECK: popfq # encoding: [0x9d]
popfq
// CHECK: movabsq $-281474976710654, %rax
// CHECK: encoding: [0x48,0xb8,0x02,0x00,0x00,0x00,0x00,0x00,0xff,0xff]
movabsq $0xFFFF000000000002, %rax
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less gross hack (having the asmmatcher handle the alias). llvm-svn: 115685
2010-10-06 05:09:45 +08:00
// CHECK: movabsq $-281474976710654, %rax
merge two tests. llvm-svn: 115170
2010-10-01 01:14:30 +08:00
// CHECK: encoding: [0x48,0xb8,0x02,0x00,0x00,0x00,0x00,0x00,0xff,0xff]
movq $0xFFFF000000000002, %rax
// CHECK: movq $-65536, %rax
// CHECK: encoding: [0x48,0xc7,0xc0,0x00,0x00,0xff,0xff]
movq $0xFFFFFFFFFFFF0000, %rax
// CHECK: movq $-256, %rax
// CHECK: encoding: [0x48,0xc7,0xc0,0x00,0xff,0xff,0xff]
movq $0xFFFFFFFFFFFFFF00, %rax
// CHECK: movq $10, %rax
// CHECK: encoding: [0x48,0xc7,0xc0,0x0a,0x00,0x00,0x00]
movq $10, %rax
// rdar://8014869
//
// CHECK: ret
// CHECK: encoding: [0xc3]
retq
// CHECK: sete %al
// CHECK: encoding: [0x0f,0x94,0xc0]
setz %al
// CHECK: setne %al
// CHECK: encoding: [0x0f,0x95,0xc0]
setnz %al
// CHECK: je 0
// CHECK: encoding: [0x74,A]
jz 0
// CHECK: jne
// CHECK: encoding: [0x75,A]
jnz 0
implement PR9264: disambiguating 'bt mem, imm' as a btl. This is reasonable to do since all bt-mem forms do the same thing. llvm-svn: 126047
2011-02-20 05:06:36 +08:00
// PR9264
btl $1, 0 // CHECK: btl $1, 0 # encoding: [0x0f,0xba,0x24,0x25,0x00,0x00,0x00,0x00,0x01]
bt $1, 0 // CHECK: btl $1, 0 # encoding: [0x0f,0xba,0x24,0x25,0x00,0x00,0x00,0x00,0x01]
merge two tests. llvm-svn: 115170
2010-10-01 01:14:30 +08:00
// rdar://8017515
btq $0x01,%rdx
// CHECK: btq $1, %rdx
// CHECK: encoding: [0x48,0x0f,0xba,0xe2,0x01]
//rdar://8017633
// CHECK: movzbl %al, %esi
// CHECK: encoding: [0x0f,0xb6,0xf0]
movzx %al, %esi
// CHECK: movzbq %al, %rsi
// CHECK: encoding: [0x48,0x0f,0xb6,0xf0]
movzx %al, %rsi
Implement enough of the missing instalias support to get aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. llvm-svn: 117901
2010-11-01 13:34:34 +08:00
// CHECK: movsbw %al, %ax
// CHECK: encoding: [0x66,0x0f,0xbe,0xc0]
movsx %al, %ax
// CHECK: movsbl %al, %eax
// CHECK: encoding: [0x0f,0xbe,0xc0]
movsx %al, %eax
// CHECK: movswl %ax, %eax
// CHECK: encoding: [0x0f,0xbf,0xc0]
movsx %ax, %eax
// CHECK: movsbq %bl, %rax
// CHECK: encoding: [0x48,0x0f,0xbe,0xc3]
movsx %bl, %rax
// CHECK: movswq %cx, %rax
// CHECK: encoding: [0x48,0x0f,0xbf,0xc1]
movsx %cx, %rax
// CHECK: movslq %edi, %rax
// CHECK: encoding: [0x48,0x63,0xc7]
movsx %edi, %rax
// CHECK: movzbw %al, %ax
// CHECK: encoding: [0x66,0x0f,0xb6,0xc0]
movzx %al, %ax
// CHECK: movzbl %al, %eax
// CHECK: encoding: [0x0f,0xb6,0xc0]
movzx %al, %eax
// CHECK: movzwl %ax, %eax
// CHECK: encoding: [0x0f,0xb7,0xc0]
movzx %ax, %eax
// CHECK: movzbq %bl, %rax
// CHECK: encoding: [0x48,0x0f,0xb6,0xc3]
movzx %bl, %rax
// CHECK: movzwq %cx, %rax
// CHECK: encoding: [0x48,0x0f,0xb7,0xc1]
movzx %cx, %rax
"mov[zs]x (mem), GR16" are not ambiguous: the mem must be 8 bits. Support this memory form. llvm-svn: 117902
2010-11-01 13:41:10 +08:00
// CHECK: movsbw (%rax), %ax
// CHECK: encoding: [0x66,0x0f,0xbe,0x00]
movsx (%rax), %ax
Implement enough of the missing instalias support to get aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. llvm-svn: 117901
2010-11-01 13:34:34 +08:00
"mov[zs]x (mem), GR16" are not ambiguous: the mem must be 8 bits. Support this memory form. llvm-svn: 117902
2010-11-01 13:41:10 +08:00
// CHECK: movzbw (%rax), %ax
// CHECK: encoding: [0x66,0x0f,0xb6,0x00]
movzx (%rax), %ax
merge two tests. llvm-svn: 115170
2010-10-01 01:14:30 +08:00
// rdar://7873482
// CHECK: [0x65,0x8b,0x04,0x25,0x7c,0x00,0x00,0x00]
movl %gs:124, %eax
// CHECK: jmpq *8(%rax)
// CHECK: encoding: [0xff,0x60,0x08]
jmp *8(%rax)
// CHECK: btq $61, -216(%rbp)
// CHECK: encoding: [0x48,0x0f,0xba,0xa5,0x28,0xff,0xff,0xff,0x3d]
btq $61, -216(%rbp)
// rdar://8061602
L1:
jecxz L1
// CHECK: jecxz L1
// CHECK: encoding: [0x67,0xe3,A]
jrcxz L1
// CHECK: jrcxz L1
// CHECK: encoding: [0xe3,A]
// PR8061
xchgl 368(%rax),%ecx
// CHECK: xchgl %ecx, 368(%rax)
xchgl %ecx, 368(%rax)
// CHECK: xchgl %ecx, 368(%rax)
// rdar://8407548
xchg 0xdeadbeef(%rbx,%rcx,8),%bl
// CHECK: xchgb %bl, 3735928559(%rbx,%rcx,8)
// PR7254
lock incl 1(%rsp)
// CHECK: lock
// CHECK: incl 1(%rsp)
Allow a slash, '/', as a prefix separator for X86. rdar://8741045 llvm-svn: 121320
2010-12-09 07:57:59 +08:00
// rdar://8741045
lock/incl 1(%rsp)
// CHECK: lock
// CHECK: incl 1(%rsp)
merge two tests. llvm-svn: 115170
2010-10-01 01:14:30 +08:00
// rdar://8033482
rep movsl
// CHECK: rep
// CHECK: encoding: [0xf3]
// CHECK: movsl
// CHECK: encoding: [0xa5]
// rdar://8403974
iret
// CHECK: iretl
// CHECK: encoding: [0xcf]
iretw
// CHECK: iretw
// CHECK: encoding: [0x66,0xcf]
iretl
// CHECK: iretl
// CHECK: encoding: [0xcf]
iretq
// CHECK: iretq
// CHECK: encoding: [0x48,0xcf]
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
// rdar://8416805
// CHECK: retw $31438
// CHECK: encoding: [0x66,0xc2,0xce,0x7a]
retw $0x7ace
// CHECK: lretw $31438
// CHECK: encoding: [0x66,0xca,0xce,0x7a]
lretw $0x7ace
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix. llvm-svn: 118903
2010-11-13 01:41:20 +08:00
// PR8592
lretq // CHECK: lretq # encoding: [0x48,0xcb]
accept lret as an alias for lretl, fixing the reopened part of PR8592 llvm-svn: 118916
2010-11-13 02:54:56 +08:00
lretl // CHECK: lretl # encoding: [0xcb]
lret // CHECK: lretl # encoding: [0xcb]
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix. llvm-svn: 118903
2010-11-13 01:41:20 +08:00
merge two tests. llvm-svn: 115170
2010-10-01 01:14:30 +08:00
// rdar://8403907
sysret
// CHECK: sysretl
// CHECK: encoding: [0x0f,0x07]
sysretl
// CHECK: sysretl
// CHECK: encoding: [0x0f,0x07]
sysretq
// CHECK: sysretq
// CHECK: encoding: [0x48,0x0f,0x07]
// rdar://8407242
push %fs
// CHECK: pushq %fs
// CHECK: encoding: [0x0f,0xa0]
push %gs
// CHECK: pushq %gs
// CHECK: encoding: [0x0f,0xa8]
pushw %fs
// CHECK: pushw %fs
// CHECK: encoding: [0x66,0x0f,0xa0]
pushw %gs
// CHECK: pushw %gs
// CHECK: encoding: [0x66,0x0f,0xa8]
pop %fs
// CHECK: popq %fs
// CHECK: encoding: [0x0f,0xa1]
pop %gs
// CHECK: popq %gs
// CHECK: encoding: [0x0f,0xa9]
popw %fs
// CHECK: popw %fs
// CHECK: encoding: [0x66,0x0f,0xa1]
popw %gs
// CHECK: popw %gs
// CHECK: encoding: [0x66,0x0f,0xa9]
// rdar://8438816
fildq -8(%rsp)
fildll -8(%rsp)
// CHECK: fildll -8(%rsp)
// CHECK: encoding: [0xdf,0x6c,0x24,0xf8]
// CHECK: fildll -8(%rsp)
// CHECK: encoding: [0xdf,0x6c,0x24,0xf8]
merge and clean up tests. llvm-svn: 115177
2010-10-01 01:24:05 +08:00
// CHECK: callq a
callq a
// CHECK: leaq -40(%rbp), %r15
leaq -40(%rbp), %r15
// rdar://8013734 - Alias dr6=db6
mov %dr6, %rax
mov %db6, %rax
// CHECK: movq %dr6, %rax
// CHECK: movq %dr6, %rax
// INC/DEC encodings.
incb %al // CHECK: incb %al # encoding: [0xfe,0xc0]
incw %ax // CHECK: incw %ax # encoding: [0x66,0xff,0xc0]
incl %eax // CHECK: incl %eax # encoding: [0xff,0xc0]
decb %al // CHECK: decb %al # encoding: [0xfe,0xc8]
decw %ax // CHECK: decw %ax # encoding: [0x66,0xff,0xc8]
decl %eax // CHECK: decl %eax # encoding: [0xff,0xc8]
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . llvm-svn: 116773
2010-10-19 08:01:44 +08:00
// rdar://8416805
// CHECK: lgdt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x50,0x04]
lgdt 4(%rax)
// CHECK: lgdt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x50,0x04]
lgdtq 4(%rax)
// CHECK: lidt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x58,0x04]
lidt 4(%rax)
// CHECK: lidt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x58,0x04]
lidtq 4(%rax)
// CHECK: sgdt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x40,0x04]
sgdt 4(%rax)
// CHECK: sgdt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x40,0x04]
sgdtq 4(%rax)
// CHECK: sidt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidt 4(%rax)
// CHECK: sidt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidtq 4(%rax)
add aliases for movs between seg registers and mem. There are multiple different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 llvm-svn: 118362
2010-11-07 06:35:34 +08:00
// rdar://8208615
mov (%rsi), %gs // CHECK: movl (%rsi), %gs # encoding: [0x8e,0x2e]
mov %gs, (%rsi) // CHECK: movl %gs, (%rsi) # encoding: [0x8c,0x2e]
implement aliases for div/idiv that have an explicit A register operand, implementing rdar://8431864 llvm-svn: 118364
2010-11-07 06:41:18 +08:00
// rdar://8431864
div %bl,%al
div %bx,%ax
div %ecx,%eax
div 0xdeadbeef(%ebx,%ecx,8),%eax
div 0x45,%eax
div 0x7eed,%eax
div 0xbabecafe,%eax
div 0x12345678,%eax
idiv %bl,%al
idiv %bx,%ax
idiv %ecx,%eax
idiv 0xdeadbeef(%ebx,%ecx,8),%eax
idiv 0x45,%eax
idiv 0x7eed,%eax
idiv 0xbabecafe,%eax
idiv 0x12345678,%eax
implement PR8524, apparently mainline gas accepts movq as an alias for movd when transfering between i64 gprs and mmx regs. llvm-svn: 119931
2010-11-21 16:18:57 +08:00
// PR8524
movd %rax, %mm5 // CHECK: movd %rax, %mm5 # encoding: [0x48,0x0f,0x6e,0xe8]
movd %mm5, %rbx // CHECK: movd %mm5, %rbx # encoding: [0x48,0x0f,0x7e,0xeb]
movq %rax, %mm5 // CHECK: movd %rax, %mm5 # encoding: [0x48,0x0f,0x6e,0xe8]
movq %mm5, %rbx // CHECK: movd %mm5, %rbx # encoding: [0x48,0x0f,0x7e,0xeb]
Testcase for r120017. llvm-svn: 120099
2010-11-25 02:03:57 +08:00
rex64 // CHECK: rex64 # encoding: [0x48]
Implement the data16 prefix. llvm-svn: 120224
2010-11-28 04:29:45 +08:00
data16 // CHECK: data16 # encoding: [0x66]
Generalize a previous change, fixing PR8855 - an valid large immediate rejected by the mc assembler. llvm-svn: 122557
2010-12-26 05:36:35 +08:00
// PR8855
movq 18446744073709551615,%rbx // CHECK: movq -1, %rbx
Fix PR8946, a missing reg/reg form of movdqu. llvm-svn: 123242
2011-01-12 01:04:55 +08:00
// PR8946
movdqu %xmm0, %xmm1 // CHECK: movdqu %xmm0, %xmm1 # encoding: [0xf3,0x0f,0x6f,0xc8]
Implement xgetbv and xsetbv. Patch by Jai Menon. llvm-svn: 126165
2011-02-22 08:35:18 +08:00
// PR8935
xgetbv // CHECK: xgetbv # encoding: [0x0f,0x01,0xd0]
xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1]
Recognize loopz and loopnz as aliases for loope and loopne. From Dimitry Andric. llvm-svn: 126168
2011-02-22 08:43:07 +08:00
// CHECK: loope 0
// CHECK: encoding: [0xe1,A]
loopz 0
// CHECK: loopne 0
// CHECK: encoding: [0xe0,A]
loopnz 0