[SystemZ] Add CodeGen support for integer vector types
This the first of a series of patches to add CodeGen support exploiting
the instructions of the z13 vector facility. This patch adds support
for the native integer vector types (v16i8, v8i16, v4i32, v2i64).
When the vector facility is present, we default to the new vector ABI.
This is characterized by two major differences:
- Vector types are passed/returned in vector registers
(except for unnamed arguments of a variable-argument list function).
- Vector types are at most 8-byte aligned.
The reason for the choice of 8-byte vector alignment is that the hardware
is able to efficiently load vectors at 8-byte alignment, and the ABI only
guarantees 8-byte alignment of the stack pointer, so requiring any higher
alignment for vectors would require dynamic stack re-alignment code.
However, for compatibility with old code that may use vector types, when
*not* using the vector facility, the old alignment rules (vector types
are naturally aligned) remain in use.
These alignment rules are not only implemented at the C language level
(implemented in clang), but also at the LLVM IR level. This is done
by selecting a different DataLayout string depending on whether the
vector ABI is in effect or not.
Based on a patch by Richard Sandiford.
llvm-svn: 236521
2015-05-06 03:25:42 +08:00
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; Test vector permutes using VPDI.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a high1/low2 permute for v16i8.
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define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vpdi %v24, %v24, %v26, 1
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3,
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i32 4, i32 5, i32 6, i32 7,
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i32 24, i32 25, i32 26, i32 27,
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i32 28, i32 29, i32 30, i32 31>
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ret <16 x i8> %ret
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}
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; Test a low2/high1 permute for v16i8.
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define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vpdi %v24, %v26, %v24, 4
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 24, i32 25, i32 26, i32 27,
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i32 28, i32 29, i32 30, i32 31,
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i32 0, i32 1, i32 2, i32 3,
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i32 4, i32 5, i32 6, i32 7>
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ret <16 x i8> %ret
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}
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; Test a low1/high2 permute for v16i8.
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define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vpdi %v24, %v24, %v26, 4
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 8, i32 9, i32 10, i32 undef,
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i32 12, i32 undef, i32 14, i32 15,
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i32 16, i32 17, i32 undef, i32 19,
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i32 20, i32 21, i32 22, i32 undef>
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ret <16 x i8> %ret
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}
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; Test a high2/low1 permute for v16i8.
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define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vpdi %v24, %v26, %v24, 1
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 16, i32 17, i32 18, i32 19,
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i32 20, i32 21, i32 22, i32 23,
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i32 8, i32 9, i32 10, i32 11,
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i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %ret
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}
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; Test reversing two doublewords in a v16i8.
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define <16 x i8> @f5(<16 x i8> %val) {
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; CHECK-LABEL: f5:
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; CHECK: vpdi %v24, %v24, %v24, 4
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val, <16 x i8> undef,
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<16 x i32> <i32 8, i32 9, i32 10, i32 11,
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i32 12, i32 13, i32 14, i32 15,
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i32 0, i32 1, i32 2, i32 3,
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i32 4, i32 5, i32 6, i32 7>
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ret <16 x i8> %ret
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}
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; Test a high1/low2 permute for v8i16.
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define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f6:
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; CHECK: vpdi %v24, %v24, %v26, 1
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; CHECK: br %r14
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%ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3,
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i32 12, i32 13, i32 14, i32 15>
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ret <8 x i16> %ret
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}
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; Test a low2/high1 permute for v8i16.
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define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f7:
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; CHECK: vpdi %v24, %v26, %v24, 4
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; CHECK: br %r14
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%ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
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<8 x i32> <i32 12, i32 13, i32 14, i32 15,
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i32 0, i32 1, i32 2, i32 3>
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ret <8 x i16> %ret
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}
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; Test a high1/low2 permute for v4i32.
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define <4 x i32> @f8(<4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f8:
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; CHECK: vpdi %v24, %v24, %v26, 1
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; CHECK: br %r14
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%ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> <i32 0, i32 1, i32 6, i32 7>
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ret <4 x i32> %ret
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}
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; Test a low2/high1 permute for v4i32.
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define <4 x i32> @f9(<4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f9:
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; CHECK: vpdi %v24, %v26, %v24, 4
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; CHECK: br %r14
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%ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> <i32 6, i32 7, i32 0, i32 1>
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ret <4 x i32> %ret
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}
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; Test a high1/low2 permute for v2i64.
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define <2 x i64> @f10(<2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f10:
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; CHECK: vpdi %v24, %v24, %v26, 1
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; CHECK: br %r14
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%ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
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<2 x i32> <i32 0, i32 3>
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ret <2 x i64> %ret
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}
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; Test low2/high1 permute for v2i64.
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define <2 x i64> @f11(<2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f11:
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; CHECK: vpdi %v24, %v26, %v24, 4
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; CHECK: br %r14
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%ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
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<2 x i32> <i32 3, i32 0>
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ret <2 x i64> %ret
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}
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2015-05-06 03:26:48 +08:00
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2015-05-06 03:27:45 +08:00
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; Test a high1/low2 permute for v4f32.
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define <4 x float> @f12(<4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f12:
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; CHECK: vpdi %v24, %v24, %v26, 1
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; CHECK: br %r14
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%ret = shufflevector <4 x float> %val1, <4 x float> %val2,
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<4 x i32> <i32 0, i32 1, i32 6, i32 7>
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ret <4 x float> %ret
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}
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; Test a low2/high1 permute for v4f32.
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define <4 x float> @f13(<4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f13:
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; CHECK: vpdi %v24, %v26, %v24, 4
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; CHECK: br %r14
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%ret = shufflevector <4 x float> %val1, <4 x float> %val2,
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<4 x i32> <i32 6, i32 7, i32 0, i32 1>
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ret <4 x float> %ret
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}
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2015-05-06 03:26:48 +08:00
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; Test a high1/low2 permute for v2f64.
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define <2 x double> @f14(<2 x double> %val1, <2 x double> %val2) {
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; CHECK-LABEL: f14:
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; CHECK: vpdi %v24, %v24, %v26, 1
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; CHECK: br %r14
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%ret = shufflevector <2 x double> %val1, <2 x double> %val2,
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<2 x i32> <i32 0, i32 3>
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ret <2 x double> %ret
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}
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; Test a low2/high1 permute for v2f64.
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define <2 x double> @f15(<2 x double> %val1, <2 x double> %val2) {
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; CHECK-LABEL: f15:
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; CHECK: vpdi %v24, %v26, %v24, 4
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; CHECK: br %r14
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%ret = shufflevector <2 x double> %val1, <2 x double> %val2,
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<2 x i32> <i32 3, i32 0>
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ret <2 x double> %ret
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}
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