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llvm-project/llvm/test/CodeGen/SystemZ/fp-cmp-04.ll

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Fix known typos Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
2014-01-25 01:20:08 +08:00
; Test that floating-point compares are omitted if CC already has the
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; right value.
;
Use the integrated assembler as default on SystemZ This was already done in clang, this commit now uses the integrated assembler as default when using LLVM tools directly. A number of test cases deliberately using an invalid instruction in inline asm now have to use -no-integrated-as. llvm-svn: 225820
2015-01-14 03:45:16 +08:00
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-integrated-as | FileCheck %s
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
declare float @llvm.fabs.f32(float %f)
; Test addition followed by EQ, which can use the CC result of the addition.
define float @f1(float %a, float %b, float *%dest) {
; CHECK-LABEL: f1:
; CHECK: aebr %f0, %f2
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: ber %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
%res = fadd float %a, %b
%cmp = fcmp oeq float %res, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %b, float *%dest
br label %exit
exit:
ret float %res
}
; ...and again with LT.
define float @f2(float %a, float %b, float *%dest) {
; CHECK-LABEL: f2:
; CHECK: aebr %f0, %f2
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: blr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
%res = fadd float %a, %b
%cmp = fcmp olt float %res, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %b, float *%dest
br label %exit
exit:
ret float %res
}
; ...and again with GT.
define float @f3(float %a, float %b, float *%dest) {
; CHECK-LABEL: f3:
; CHECK: aebr %f0, %f2
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: bhr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
%res = fadd float %a, %b
%cmp = fcmp ogt float %res, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %b, float *%dest
br label %exit
exit:
ret float %res
}
; ...and again with UEQ.
define float @f4(float %a, float %b, float *%dest) {
; CHECK-LABEL: f4:
; CHECK: aebr %f0, %f2
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: bnlhr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
%res = fadd float %a, %b
%cmp = fcmp ueq float %res, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %b, float *%dest
br label %exit
exit:
ret float %res
}
; Subtraction also provides a zero-based CC value.
define float @f5(float %a, float %b, float *%dest) {
; CHECK-LABEL: f5:
; CHECK: seb %f0, 0(%r2)
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: bnher %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
[SystemZ] Test case formatting fixes Fix systematically wrong whitespace from a prior automated change. NFC. llvm-svn: 337542
2018-07-20 20:12:10 +08:00
%cur = load float, float *%dest
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
%res = fsub float %a, %cur
%cmp = fcmp ult float %res, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %b, float *%dest
br label %exit
exit:
ret float %res
}
; Test the result of LOAD POSITIVE.
define float @f6(float %dummy, float %a, float *%dest) {
; CHECK-LABEL: f6:
; CHECK: lpebr %f0, %f2
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: bhr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
%res = call float @llvm.fabs.f32(float %a)
%cmp = fcmp ogt float %res, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %res, float *%dest
br label %exit
exit:
ret float %res
}
; Test the result of LOAD NEGATIVE.
define float @f7(float %dummy, float %a, float *%dest) {
; CHECK-LABEL: f7:
; CHECK: lnebr %f0, %f2
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: blr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
%abs = call float @llvm.fabs.f32(float %a)
[SystemZ] Use fneg in test cases Now that we have fneg, prefer using it over "fsub -0.0, ...". This helps in particular with strict FP tests, as fneg does not raise any exceptions.
2019-11-21 02:07:03 +08:00
%res = fneg float %abs
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
%cmp = fcmp olt float %res, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %res, float *%dest
br label %exit
exit:
ret float %res
}
; Test the result of LOAD COMPLEMENT.
define float @f8(float %dummy, float %a, float *%dest) {
; CHECK-LABEL: f8:
; CHECK: lcebr %f0, %f2
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: bler %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
[SystemZ] Use fneg in test cases Now that we have fneg, prefer using it over "fsub -0.0, ...". This helps in particular with strict FP tests, as fneg does not raise any exceptions.
2019-11-21 02:07:03 +08:00
%res = fneg float %a
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
%cmp = fcmp ole float %res, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %res, float *%dest
br label %exit
exit:
ret float %res
}
; Multiplication (for example) does not modify CC.
define float @f9(float %a, float %b, float *%dest) {
; CHECK-LABEL: f9:
; CHECK: meebr %f0, %f2
; CHECK-NEXT: ltebr %f0, %f0
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: blhr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
%res = fmul float %a, %b
%cmp = fcmp one float %res, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %b, float *%dest
br label %exit
exit:
ret float %res
}
; Test a combination involving a CC-setting instruction followed by
; a non-CC-setting instruction.
define float @f10(float %a, float %b, float %c, float *%dest) {
; CHECK-LABEL: f10:
; CHECK: aebr %f0, %f2
; CHECK-NEXT: debr %f0, %f4
; CHECK-NEXT: ltebr %f0, %f0
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: bner %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
%add = fadd float %a, %b
%res = fdiv float %add, %c
%cmp = fcmp une float %res, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %b, float *%dest
br label %exit
exit:
ret float %res
}
; Test a case where CC is set based on a different register from the
; compare input.
define float @f11(float %a, float %b, float %c, float *%dest1, float *%dest2) {
; CHECK-LABEL: f11:
; CHECK: aebr %f0, %f2
; CHECK-NEXT: sebr %f4, %f0
[SystemZ] Enable machine scheduler. The machine scheduler (before register allocation) is enabled by default for SystemZ. The SelectionDAG scheduling preference now becomes source order scheduling (was regpressure). Review: Ulrich Weigand https://reviews.llvm.org/D37977 llvm-svn: 315063
2017-10-06 21:59:28 +08:00
; CHECK-DAG: ste %f4, 0(%r2)
; CHECK-DAG: ltebr %f0, %f0
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: ber %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
%add = fadd float %a, %b
%sub = fsub float %c, %add
store float %sub, float *%dest1
%cmp = fcmp oeq float %add, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %sub, float *%dest2
br label %exit
exit:
ret float %add
}
; Test that LER gets converted to LTEBR where useful.
define float @f12(float %dummy, float %val, float *%dest) {
; CHECK-LABEL: f12:
; CHECK: ltebr %f0, %f2
; CHECK-NEXT: #APP
; CHECK-NEXT: blah %f0
; CHECK-NEXT: #NO_APP
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: blr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
call void asm sideeffect "blah $0", "{f0}"(float %val)
%cmp = fcmp olt float %val, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %val, float *%dest
br label %exit
exit:
ret float %val
}
; Test that LDR gets converted to LTDBR where useful.
define double @f13(double %dummy, double %val, double *%dest) {
; CHECK-LABEL: f13:
; CHECK: ltdbr %f0, %f2
; CHECK-NEXT: #APP
; CHECK-NEXT: blah %f0
; CHECK-NEXT: #NO_APP
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: blr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
call void asm sideeffect "blah $0", "{f0}"(double %val)
%cmp = fcmp olt double %val, 0.0
br i1 %cmp, label %exit, label %store
store:
store double %val, double *%dest
br label %exit
exit:
ret double %val
}
; Test that LXR gets converted to LTXBR where useful.
define void @f14(fp128 *%ptr1, fp128 *%ptr2) {
; CHECK-LABEL: f14:
; CHECK: ltxbr
; CHECK-NEXT: dxbr
; CHECK-NEXT: std
; CHECK-NEXT: std
; CHECK-NEXT: mxbr
; CHECK-NEXT: std
; CHECK-NEXT: std
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: blr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
[SystemZ] Test case formatting fixes Fix systematically wrong whitespace from a prior automated change. NFC. llvm-svn: 337542
2018-07-20 20:12:10 +08:00
%val1 = load fp128, fp128 *%ptr1
%val2 = load fp128, fp128 *%ptr2
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
%div = fdiv fp128 %val1, %val2
store fp128 %div, fp128 *%ptr1
%mul = fmul fp128 %val1, %val2
store fp128 %mul, fp128 *%ptr2
%cmp = fcmp olt fp128 %val1, 0xL00000000000000000000000000000000
br i1 %cmp, label %exit, label %store
store:
call void asm sideeffect "blah", ""()
br label %exit
exit:
ret void
}
; Test a case where it is the source rather than destination of LER that
; we need.
define float @f15(float %val, float %dummy, float *%dest) {
; CHECK-LABEL: f15:
; CHECK: ltebr %f2, %f0
; CHECK-NEXT: #APP
; CHECK-NEXT: blah %f2
; CHECK-NEXT: #NO_APP
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: blr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
call void asm sideeffect "blah $0", "{f2}"(float %val)
%cmp = fcmp olt float %val, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %val, float *%dest
br label %exit
exit:
ret float %val
}
; Test a case where it is the source rather than destination of LDR that
; we need.
define double @f16(double %val, double %dummy, double *%dest) {
; CHECK-LABEL: f16:
; CHECK: ltdbr %f2, %f0
; CHECK-NEXT: #APP
; CHECK-NEXT: blah %f2
; CHECK-NEXT: #NO_APP
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: blr %r14
[SystemZ] Optimize floating-point comparisons with zero This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. llvm-svn: 187883
2013-08-07 19:10:06 +08:00
; CHECK: br %r14
entry:
call void asm sideeffect "blah $0", "{f2}"(double %val)
%cmp = fcmp olt double %val, 0.0
br i1 %cmp, label %exit, label %store
store:
store double %val, double *%dest
br label %exit
exit:
ret double %val
}
[SystemZ] Use LOAD AND TEST for comparisons with -0 ...since it os equivalent to comparison with +0. llvm-svn: 196580
2013-12-06 17:59:12 +08:00
; Repeat f2 with a comparison against -0.
define float @f17(float %a, float %b, float *%dest) {
; CHECK-LABEL: f17:
; CHECK: aebr %f0, %f2
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: blr %r14
[SystemZ] Use LOAD AND TEST for comparisons with -0 ...since it os equivalent to comparison with +0. llvm-svn: 196580
2013-12-06 17:59:12 +08:00
; CHECK: br %r14
entry:
%res = fadd float %a, %b
%cmp = fcmp olt float %res, -0.0
br i1 %cmp, label %exit, label %store
store:
store float %b, float *%dest
br label %exit
exit:
ret float %res
}
[SystemZ] Optimize fcmp X, 0 in cases where X is also negated In such cases it's often better to test the result of the negation instead, since the negation also sets CC. llvm-svn: 197032
2013-12-11 19:45:08 +08:00
; Test another form of f7 in which the condition is based on the unnegated
; result. This is what InstCombine would produce.
define float @f18(float %dummy, float %a, float *%dest) {
; CHECK-LABEL: f18:
; CHECK: lnebr %f0, %f2
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: blr %r14
[SystemZ] Optimize fcmp X, 0 in cases where X is also negated In such cases it's often better to test the result of the negation instead, since the negation also sets CC. llvm-svn: 197032
2013-12-11 19:45:08 +08:00
; CHECK: br %r14
entry:
%abs = call float @llvm.fabs.f32(float %a)
[SystemZ] Use fneg in test cases Now that we have fneg, prefer using it over "fsub -0.0, ...". This helps in particular with strict FP tests, as fneg does not raise any exceptions.
2019-11-21 02:07:03 +08:00
%res = fneg float %abs
[SystemZ] Optimize fcmp X, 0 in cases where X is also negated In such cases it's often better to test the result of the negation instead, since the negation also sets CC. llvm-svn: 197032
2013-12-11 19:45:08 +08:00
%cmp = fcmp ogt float %abs, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %res, float *%dest
br label %exit
exit:
ret float %res
}
; Similarly for f8.
define float @f19(float %dummy, float %a, float *%dest) {
; CHECK-LABEL: f19:
; CHECK: lcebr %f0, %f2
[SystemZ] Implement conditional returns Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
2016-04-08 00:11:44 +08:00
; CHECK-NEXT: bler %r14
[SystemZ] Optimize fcmp X, 0 in cases where X is also negated In such cases it's often better to test the result of the negation instead, since the negation also sets CC. llvm-svn: 197032
2013-12-11 19:45:08 +08:00
; CHECK: br %r14
entry:
[SystemZ] Use fneg in test cases Now that we have fneg, prefer using it over "fsub -0.0, ...". This helps in particular with strict FP tests, as fneg does not raise any exceptions.
2019-11-21 02:07:03 +08:00
%res = fneg float %a
[SystemZ] Optimize fcmp X, 0 in cases where X is also negated In such cases it's often better to test the result of the negation instead, since the negation also sets CC. llvm-svn: 197032
2013-12-11 19:45:08 +08:00
%cmp = fcmp oge float %a, 0.0
br i1 %cmp, label %exit, label %store
store:
store float %res, float *%dest
br label %exit
exit:
ret float %res
}